Noise-Aware FET Circuit Design Based on C/ID-Invariant

Abstract

This article presents an analytical approach, supported by experimental data, to design analog circuits for given noise and speed specifications. As an extension to traditional design methodologies, i.e., Inversion Coefficient (IC) and gm/ID (GmID), the proposed approach aims to gain more in-depth insight, while providing appropriate analytical means for circuit design, at lower levels of computing complexity. Based on a recently proposed design approach, the C/ID method relies on device characteristic capacitance, i.e., CS = CS/ID as an invariant, where CS refers to the Field-Effect Transistor (FET) device self-loading capacitance. C/ID provides the opportunity to derive closed-form solutions to some key design optimization problems such as power versus Gain Bandwidth (GBW) and noise trade-offs. Examples for common-source amplifiers and Ring Oscillators (RO) have been provided. A set of current-steering ROs has been designed and fabricated in 0.18 lm technology based on the proposed flow. The circuit Phase Noise (PN) was characterized and compared to the predictions of the proposed design methodology, demonstrating favorable matching.