Design For Testability Research Articles

Research on Testability Design and Evaluation Method for Ship Electromechanical Equipment

As a relatively large amount of electromechanical equipment was installed in the ship systems, it was difficult to position and eliminate the faults of the M&E equipment if any. Hence, there was a need to improve the fault detection and isolation capabilities of the equipment depending on testability design and to develop the corresponding fault diagnosis system when necessary, thus improving the overall availability of the equipment and ensuring that the ship could successfully complete the missions. In view of the above requirements, this paper, taking the most representative M&E equipment - pump set on the ship as a research object, gave the testability design process of the M&E equipment - pump set for product development, illustrated the equipment testability design methods from 4 aspects (namely determination of equipment testability and fault diagnosis system requirements, testability analysis & design, comprehensive fault diagnosis system design and testability verification process design), specified the testability design & monitoring object selection principles and fault characteristic determination methods, and finally provided the testability design evaluation methods for the M&E equipment for verifying whether the testability requirements were met.

Crash analysis of a passenger car bumper assembly to improve design for impact test

The bumper of a car is an essential component of the car it helps in reducing the impact energy by absorbing it and hence it minimizes the damage to the vehicle and the passenger in the car and improves the safety. Over the past few years, the design and the use of the material for bumper have been upgrading with improvements in the design and use of quality material to make the bumper of a passenger car. The Majority of passenger vehicle accidents occur on the front side. So to absorb the impact force and the energy released during the collision of a vehicle the material and the design of the bumper should be considered to improve safety to the passengers in the car and reduce the damage of the body parts. Proper selection of material and design of bumper plays an important role. During the design of the bumper the cost of the material and the weight ratio has been considered so that it is cost efficient and low repair cause during the usage. In the current paper, the passenger vehicle bumper is being tested with three different materials, namely, Aluminium alloy, Thermoplastic and Chromium coated mild steel at three various speeds by gradually increase the speed of the car. Firstly at the pace of 40 km per hour, next at speed 60 km/h, and then finally at the speed of 80 km/per h. The deformation of the body, the stress at various speed and the strain are analyzed so that the appropriate material is taken manufacture the bumper of the car. 3D models are presented in the CAD software and also inspection carried out in Analysis software.

A Dynamic-Key Based Secure Scan Architecture for Manufacturing and In-Field IC Testing

The design for testability (DFT) technology based on scan chains is widely used in industry to increase the testability of circuits. However, it also leads to a potential security problem that attackers can use scan chains as a backdoor to attack a system. Common methods to defend such attacks include disabling the scan chain after manufacturing test or employing some secret keys to encrypt/decrypt scan data or to verify the identities of users. The former would make in-field testing impossible and the latter would require storing keys in memory which might also undergo high risk of memory attacks. In this paper we propose a dynamic-key based secure scan architecture that works together with an intrinsic Physical Unclonable Function (PUF) of chips to defend both scan-based and memory attacks while facilitating both manufacturing and in-field testing. A system equipped with this secure architecture will shift out true circuit responses only when legal test patterns are shifted into the scan chains. Moreover, no test key will be stored in memory, hence no memory attacks are possible. We also leverage the PUF to distinct the legal test patterns for different manufactured chips so as to further protect chips. Analysis results show that our protection scheme can achieve a very high security level without sacrificing system performance, testability and diagnosability.

Bayesian Network Model Test Configuration Method based on Genetic and Binary Discrete Particle Swarm Combination Algorithm

Test configuration is an important part in the process of testability design. Most of the existing test configuration methods are based on multi-signal flow diagram model and adopt genetic algorithm or particle swarm optimization (pso). However, there are many problems in this solution. First of all, the multi-signal flow diagram model has poor ability to express uncertain information, low model accuracy, large deviation in the calculation of testability indicators, and the model does not have the ability to learn and update. Secondly, the efficiency of genetic algorithm is low and the computation time is long, while the binary discrete particle swarm optimization algorithm is easy to fall into the local optimal. To solve the above two problems, a test configuration method based on the hybrid algorithm of genetic -binary discrete particle swarm optimization is proposed. This method can combine the global search ability of genetic algorithm with the optimal speed of binary particle swarm optimization, and use the bayesian network model to calculate more accurate testability indexes. It is proved that the algorithm can make full use of the high-precision information provided by the model, and the calculation speed is fast.And it is not easy to fall into the local optimal solution.

Research on the Testability Design System of Airborne System

Research on the Testability Design System of Airborne System

Integrated Stateflow-based simulation modelling and testability evaluation for electronic built-in-test (BIT) systems

The simulation modelling for built-in test (BIT) system is an important approach to analyse the testability and evaluate the BIT performance. However, existing simulation modelling methods cannot satisfy the simulation requirements of abundant testability design factors, especially for the fault and interference injection and the test logic of BIT. Therefore, this paper proposes an integrated modelling and simulation method for BIT system based on Stateflow. This simulation modelling method has three highlights. 1) this method can dynamically realise the fault transmission and BIT monitoring processes under test. 2) this method can generate diagnostic knowledge through the fault injection function. 3) this method can calculate BIT performance metrics, especially the false alarm probability to realise more comprehensive testability evaluation. This paper firstly presents the BIT detection, isolation, and false alarm reduction logics and model formulation. Then the testability metrics and d-matrix calculation models are presented. Finally, the proposed method is applied in an example of an electronic secondary power conversion board. The testability metrics are reported by the simulation model, which comply with the real hardware analysis and experiment.

An Efficient VLSI Test Data Compression Scheme for Circular Scan Architecture Based on Modified Ant Colony Meta-heuristic

A new test data compression scheme for circular scan architecture is proposed in this paper. A stochastic heuristic based bio-inspired optimization approach namely ant colony algorithm (ACO) is applied after modification and customization to improve compression efficiency. In circular scan architecture, test data compression is achieved by updating the conflicting bits between the most recently captured response and test vector to be applied next. The quantity of conflicting bits also manifests the Hamming distance between the most recently captured response and the next test vector. A significant reduction in test data volume and test application time is achieved by reducing Hamming distance. The problem is renovated as a traveling salesman problem (TSP). The test vectors are presumed as cities and Hamming distance between a pair of test vectors is treated as intercity distance and a modified ACO algorithm in combination with mutation operator is applied here to resolve this combinatorial optimization problem. The experimental results confirm the efficacy of this approach. An average improvement of 6.36% in compression ratio and 4.77% in test application time is achieved. The exhibited technique sustains an optimal level of performance without incurring any extra DFT (design for testability) cost.

VLSI Implementation of Linear Feedback Shift Register (LFSR) based Test Pattern Generator for Pseudo Exhaustive Testing

Advanced strides of improvement in programmable logic density, enhancements in speed and hardware description language (HDL) are empowering design engineers to implement highly performing and testable digital systems. Linear feedback shift registers (LFSR) are the critical elements in the testing and self testing of contemporary complex electronic systems like processors, Built-in-self-test (BIST) controllers and integrated circuits (ICs) etc. Fundamentally BIST is a Design-for-Testability (DFT) technique meant to configure testing functions physically with the circuit under test (CUT). To enhance the percentage of fault coverage as a part of BIST operations (testing the IC), LFSRs are deployed (as test pattern generator) to generate the test vectors inside logic BIST for testing digital systems. Proposed work is focused upon designing a fast adder based variable length pseudorandom binary sequence pattern generator (PRBSPG) and experimental validations. LFSR possess characteristics of high speed, better encoding efficiency, high fault coverage, low test volume data and low power consumption specially suitable in processing environment where uniform distribution random numbers are required. Verilog HDL is employed for structuring the modular design units while Xilinx ISE tool is deployed for validating the proposed LFSR design work and associated modular units.

Defect Analysis and Parallel Testing for 3D Hybrid CMOS-Memristor Memory

CMOS Molecular (CMOL) architecture, which can alleviate the sneak path problem of one memristor (1R) crossbars and limit its power consumption, can be used in a large-scale memory system. In this article, we analyze the electrical defects in a CMOL circuit including open and bridge. A parallel March-like test algorithm is presented for the CMOL architecture, which covers the faults caused by the open and bridge defects and parametric variations during its fabrication. Analysis results show that the test time of the proposed test algorithm is reduced significantly compared with the enhanced methods of March-MOM and March C* for CMOL architectures. The write time is reduced approximately 5 <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</i> /4× and <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</i> ×, respectively, where <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</i> is the number of memristors attached to a nanowire segment. The read time is also reduced drastically. Finally, a design for testability (DFT) architecture is proposed to adapt the parallel March-like test algorithm. In compare with the short write time testing scheme, the proposed DFT can achieve 35.4 percent of reduction in area overhead, with 14.52 percent more power overhead kept the same delay in a CMOL circuit with 64 memory cells.

Reduction of Test Time using Multiple Test Control Point Insertion for 7nm Technology Node

Test time reduction is a prominent challenge in scan based Design For Testability (DFT) architectures for cost effective test. Reliability and testability both are main objectives for DFT in today’s VLSI design. In this paper, we have proposed multiple standard test control point insertion technique for 7nm technology node. The design was tested on 7828 sequential cells. We have compared results of following three Design Rule Check (DRC) (1) Scan DRC (2) Clock Scan DRC (3) Multiple standard test control point insertion DRC. We have used software tool Synopsys TetraMAX ATPG, Synopsys DFTMAX and Synopsys DFT compiler to verify the design. It has been observed that multiple standard test control point insertion DRC takes minimum time to check design of 7828 sequential cells.

Monitoring Aging Defects in STT-MRAMs

Identifying manufacturing defects in magnetic tunnel junction (MTJ) device is crucial for the yield and reliability of spin-torque-transfer (STT) magnetic random-access memory (MRAM) arrays. Several of the MTJ defects result inparametric deviations of the device that deteriorate over time. In this article, we present the design-for-testability (DFT) scheme for monitoring the electrical parameter deviations occurring due to the defect formation over time. A programmable DFT scheme was implemented for a subarray in 65-nm CMOS technology to evaluate the feasibility of the test scheme. The scheme utilizes the read sense path to compare the bit-cell electrical parameters against known DFT cell’s characteristics. Built-in-self-test (BIST) methodology is utilized to trigger the onset of the fault once the device parameter crosses a threshold value. We demonstrate the operation and evaluate the accuracy of detection with the proposed scheme. The DFT scheme can be exploited for monitoring aging defects, modeling their behavior and optimization of the fabrication process.

A compact, highly stable spectral shearing interferometer to accurately reconstruct ultrafast laser fields

This paper presents a compact design for spectral shearing interferometry to reconstruct an ultrafast electric-field (SPIDER) with a high signal-to-noise ratio (SNR) and stability. Compared experimentally with the traditional SPIDER based on a Michelson interferometer (MI), this design can improve the SNR by a factor of 3.7 in a 25 dB BW region. Using the material dispersions of 6 mm BK7 plates as a target, the phase errors between the measured and theoretical values are less than 2.6 mrad, which is improved by a factor of ~4 from 10.3 mrad measured with the MI-based version. Even for a 1 mm fused silica plate, the measured phase errors are less than 2.1 mrad from the calculated values. Using this design for a 3-day test of our ultrashort pulse laser system, the variation in the output pulse width from the first to the third day is only 1.5%. We attribute this excellent performance to the common-path and all-transmission design of the test pulse pair, giving the design superior capacity against external disturbances. Our design can also work with the two-step phase-shift (TSPS) method to improve its measurement of the plulses with complex temporal/spectral structures.

A Guaranteed Secure Scan Design Based on Test Data Obfuscation by Cryptographic Hash

Design-for-testability (DfT) techniques have been widely adopted into the integrated circuit (IC) design process to facilitate manufacture testing. The scan-based DfT architecture is a popular DfT feature that provides full testability for the circuit under test. However, this turns into a double-edged sword for some ICs such as cryptographic chips because scan design could be used as a side channel to access the intermediate encryption results, with which the cipher key can be deduced easily. To resist such scan-based side-channel attacks, many countermeasures are proposed to obfuscate the test data in scan chain. Unfortunately, most of the obfuscation logic, due to the performance and resource constraints, cannot be proven to be irreversible and hence suffers a high risk for the correct test data being derived from the obfuscated output. In this article, we propose to utilize the cryptographic hash module for some post-processing of the test responses in order to secure the scan design. Our approach has several clear advantages over existing ones. First, the security is guaranteed based on the preimage resistance of cryptographic hash function and the introduced salt information and data collection scheme. Second, it incurs low overhead because the hash module is normally available on the IC, in particular, those where security is important. Finally, full testability is retained as we are not modifying any test input. We present the implementation of the proposed secure design, report the experimental results, and demonstrate that our approach can resist all known scan-based side-channel attacks with negligible overhead while maintaining the testability and other testing performances.

Pemanfaatan Mikroba Tanah dalam Pembuatan Pupuk Organik serta Peranannya terhadap Tanah Aluvial dan Pertumbuhan Bibit Tanaman Kakao

The use of microorganisms and organic materials in agriculture because it can increase the availability of soil nutrients and absorption by plants and form soil structures becomes looser. The purpose of this study was to obtain the most effective types of decomposer microorganisms and the most appropriate organic fertilizer (compost) to improve the physical, chemical and biological properties of alluvial soils and their role in plants in cocoa seedlings. The research was conducted in the Laboratory of Soil, Greenhouses and experimental gardens of the Agricultural Polytechnic State Payakumbuh Tanjung Pati Kabupaten Lima Puluh Kota. The study uses experimental methods. The study used a factorial randomized block design on soil tests and a complete randomized design for the cacao seedling test. Parameters observed were alluvial soil pH, N-total alluvial soil, P-available alluvial soil, K-exchangeable alluvial soil, alluvial soil volume weight, the total population of alluvial soil bacteria, plant height of cocoa seedlings, number of leaves of cocoa seedlings, stem diameter of cocoa seedlings, dry weight of cacao seed stover. The results of the study there were no differences in the treatment of the type of compost and the type of microorganisms to the pH value of the soil. Types of microorganisms with the type of compost can increase the total N content in alluvial soil. The use of compost types and types of microorganisms had a significantly different effect on the value of soil volume weight, P-available, K-exchangeable, and the total population of alluvial soil bacteria. Treatment of Type of Compost Tithonia and Types of Pseudomonas fluorescens + Trichoderma harzianum microorganisms have the best influence on soil test variables. The application of cacao seedlings at the dose of Tithonia compost 1.25 kg/polybag provides the best growth.&#x0D; Keywords: Alluvial soil, cocoa seedlings, compost, microorganisms

Efficient Key-Gate Placement and Dynamic Scan Obfuscation Towards Robust Logic Encryption

Logic encryption has emerged to be a potential solution to the problem of Intellectual Property (IP)-Piracy and counterfeiting. However, in the recent past, several attacks have been mounted on existing logic encryption strategies to extract the secret key. SAT attack, the most predominant one among them, exploits the unprotected Design-for-Testability (DfT) infrastructure as a backdoor to launch attacks on sequential circuits. Protecting the DfT infrastructure is of paramount importance to ensure the security of an Integrated Chip (IC). In this paper, we propose a new logic encryption scheme which dynamically obfuscates the scan operation for an unauthorized attempt of scan access. A detailed security analysis on the proposed secure DfT infrastructure demonstrates its ability to thwart SAT attack without compromising the testability of the design. A methodical key-gate placement strategy enables the proposed scheme to eliminate the leakage of key information through weak key-gate locations, offering protection against path sensitization and logic cone based attacks. Unlike other state-of-the-art SAT preventive schemes, our proposed method does not suffer from poor output corruption, which is a fundamental requirement of a logic encryption scheme.

Prognostics and health management technology for radar system

Information-based war in the future has a higher requirement to the maintenance and support ability of radar system. Prognostics and Health Management(PHM) technology represents the research hotspot of maintenance system, and following key techniques need to be resolved to research on the radar PHM technology such as the acquirement and selection of health information and fault signs of a radar’s electronical components, mass data warehousing and mining, fusion of multi-source test data and multi-field characteristic information, failure model building and forecasting, automatic decision-making on maintenance, and at the same time improving the self built-in test abilities of radar’s components based on the optimization of Design For Testability(DFT). The radar PHM technology has the trend of “built-in to integrate”, “together with DFT” and “long-distance and distributed”. However, subjected to radar’s complexity and current PHM technique level, radar PHM engineering still meets many challenges, but has bright future.

NHPP Testability Growth Model Considering Testability Growth Effort, Rectifying Delay, and Imperfect Correction

Over the last several years, many testability growth models (TGMs) have been developed to greatly facilitate engineers and managers in tracking and measuring the growth of testability as system is being improved. Most TGMs consider only one or two variation patterns of the aspects, such as the testability growth effort (TGE) in testability design limitation (TDL) identification, the rectifying delay and the new TDL introduction in TDL correction. However, the ignorance of such joint consideration may lead to a lower fitting ability to the fault detection/isolation data. Inspired by the counting idea of non-homogeneous Poisson process (NHPP), a NHPP based testability growth model (TGM) considering the recurrence rate function (RRF) of TDL identification, TDL correction and new TDL introduction is proposed for the foundation of TGM. A real data set of a missile control system is used to validate the above TGMs in fitting ability, estimation accuracy and prediction capability. Results show that the bell-shaped curve can fit the identification process and rectifying delay process of TDL well, and the imperfect correction of TDL really exists in the testability growth test (TGT), and the inflected s-shaped and Gamma function based TGM gives good capacity to the real data set.

Invisible-Scan: A Design-for-Testability Approach for Functional Test Sequences

Functional test sequences can detect defects that are not detected by scan-based tests, but overall, achieve a lower gate-level fault coverage than scan-based tests. Design-for-testability (DFT) approaches for functional test sequences cause the sequences to deviate from functional operation conditions in arbitrary ways over the entire design. This paper introduces the concept of invisible-DFT as a DFT approach for functional test sequences, where the effects of activating the DFT logic are confined to selected logic blocks. This paper develops an invisible-scan approach. Considering a single logic block, the procedure described in this paper inserts scan shift cycles into a functional test sequence while maintaining the same primary input and output sequences for the logic block. This makes the activation of the DFT logic invisible to other logic blocks. The procedure allows a limited number of primary output vectors to be corrected for this purpose. Experimental results are presented to demonstrate the increase in fault coverage that can be achieved by invisible-scan.

Efek Ekstrak Etanol Daun Kelor (Moringa oleifera, Lamk.) Pada Mencit Model Demensia: Kajian Memori Spasial, Kadar Malondialdehid Dan Jumlah Sel Piramidal Hipokampus Area CA1 Dan CA2-CA3

ABSTRAK&#x0D; penyakit sel-sel saraf di otak, akibat hipokampus yang rusak oleh radikal bebas. EEDK (Ekstrak etanol daun kelor) (Moringa oleifera, Lamk.) mengandung phytochemicals, karoten, vitamin, mineral, asam amino, flavonoid dan phenolic, terbukti mengurangi kerusakan oksidatif dan defisit memori. Penelitian ini bertujuan mengetahui efek EEDK terhadap memori spasial, kadar MDA, jumlah sel piramidal hipokampus yang rusak area CA1,CA2-CA3 dan gambaran histopatologi mencit.&#x0D; Rancangan penelitian ini pre test and post test control group design untuk uji memori spasial dan post test control group design untuk uji kadar MDA, jumlah sel piramidal hipokampus dan gambaran histopatologi. Menggunakan 30 ekor mencit terdiri dari 6 kelompok, per kelompok ada 5 ekor mencit, yaitu kelompok kontrol normal, kontrol positif, kontrol negatif, kelompok EEDK 100, 200, dan 400 mg/kgBB, semua diinduksi Pb asetat 50 mg/KgBB kecuali pada kelompok normal. Kontrol positif diobati kuersetin 50 mg/kgBB, sedangkan kontrol negatif tidak diobati. Data uji memori diperoleh dari uji Morris water maze pra dan paska perlakuan, data status antioksidan diperoleh dari uji kadar MDA dan data gambaran histopatologi diperoleh dari perhitungan jumlah sel pyramidal. Analisis data menggunakan repeated measures ANOVA dan ANOVA dengan Post Hoc LSD.&#x0D; Hasil penelitian menunjukkan waktu latensi, uji kadar MDA dan pemeriksaan histopatologi otak terdapat perbedaan bermakna antara kelompok kontrol negatif dengan kelompok EEDK. Pemberian EEDK 400 mg/kgBB paling efektif memperbaiki memori spasial, menurunkan kadar MDA, dan mencegah kerusakan sel piramidal hipokampus area CA1, CA2-CA3.

Design of testable reversible latches by using a novel efficient implementation of Fredkin gate

ABSTRACTEnergy dissipation caused by information loss in irreversible computations will be an important limitation for the development of nano-scale circuits in the near future. Reductions in energy dissipation comprise one of the important goals of nanotechnology-based methods, including Quantum dot Cellular Automata (QCA), and so it is desirable to consider reversibility in the design of QCA circuits. In this research, a novel reversible Fredkin gate based on QCA is proposed, which is more efficient and less complex than the conventional Fredkin gate. Conservative reversible logic is parity preserving; hence, any permanent or transient fault can be caused a mismatch between the inputs and the outputs and can be concurrently detected if a reversible circuit is implemented with the conservative Fredkin gate. A single missing/additional cell defect is investigated in the proposed Fredkin gate and fault patterns are presented. To demonstrate the efficiency of the proposed design, some testable reversible sequential elements, such as D-latch, JK-latch, T-latch and SR-latch, are designed by using it. Our proposed concurrent testable designs greatly reduce the occupied area and maximise the circuit density in comparison with previously reported designs. The proposed designs are simulated and verified using QCA Designer ver.2.0.3 and HDLQ.