Abstract
Identifying manufacturing defects in magnetic tunnel junction (MTJ) device is crucial for the yield and reliability of spin-torque-transfer (STT) magnetic random-access memory (MRAM) arrays. Several of the MTJ defects result inparametric deviations of the device that deteriorate over time. In this article, we present the design-for-testability (DFT) scheme for monitoring the electrical parameter deviations occurring due to the defect formation over time. A programmable DFT scheme was implemented for a subarray in 65-nm CMOS technology to evaluate the feasibility of the test scheme. The scheme utilizes the read sense path to compare the bit-cell electrical parameters against known DFT cell’s characteristics. Built-in-self-test (BIST) methodology is utilized to trigger the onset of the fault once the device parameter crosses a threshold value. We demonstrate the operation and evaluate the accuracy of detection with the proposed scheme. The DFT scheme can be exploited for monitoring aging defects, modeling their behavior and optimization of the fabrication process.
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