This work presents an efficient test technique for detecting resistive short defects in STT-MRAM arrays. The proposed technique is based on monitoring the current mismatch flowing into and out of the cell caused by a weak or strong short defect. This technique is used to propose a low area overhead Design-for-Testability (DFT) circuit to employ in STT-MRAM arrays to distinguish defect-free cells from faulty ones. The operation of the proposed test approach is resilient to the parameter uncertainties of the array circuit induced by process variations. The variations, however, may lower defect detection ranges. The efficacies of the proposed DFT technique under the nominal and the process variation cases are studied. Simulation results indicate that the proposed DFT circuit reduces the number of test escapes and improves the fault coverage by a factor of at least 10 × ( 5 ×) under short defect to ground (short defect to V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> ) cases compared to the corresponding maximum ones detected by conventional test schemes. The technique works through a single read operation with a negligible area overhead, especially, in large size arrays.