A Comprehensive Comparison Between Design for Testability Techniques for Total Dose Testing of Flash-Based FPGAs

Abstract

A comprehensive comparison between different design for testability (DFT) techniques for total-ionizing-dose (TID) testing of flash-based field-programmable gate arrays (FPGAs) is made to help designers choose the best suitable DFT technique depending on their application. The comparison includes muxed D scan, clocked scan, and enhanced scan DFT techniques. The comparison is done using ISCAS'89 benchmarks circuits. Points of comparisons include FPGA resources utilization, difficulty in design bring-up, added delay by DFT logic, and robust testable paths in each technique. We verified the results of each technique experimentally using Microsemi ProASIC3 FPGA's and Cobalt 60 facility. The experimental results show a close total-dose failure level for all techniques when using worst-case test vectors (WCTVs) in total-dose testing of FPGA devices.