Fault Modeling and Worst-Case Test Vector Generation for Flash-Based FPGA’s Exposed to Total Dose

Abstract

We analyzed the delay failure induced in flash-based field-programmable gate arrays (FPGAs) exposed to total-ionizing dose. We developed a novel cell-level fault model for such delay failure. We introduced a novel methodology for identifying worst case test vectors (WCTVs) for flash-based FPGA devices exposed to total-ionizing dose based on the developed fault model for delay failure. We introduced a novel methodology to identify WCTVs for flash-based FPGAs using commercially available design and automatic test pattern generation tools. We validated the delay fault model using Microsemi ProASIC3 FPGAs and Cobalt 60 facility. The experimental results also show significant impact on the total-dose failure levels when using WCTVs.