Worst-Case Test Vectors for Logic Faults Induced by Total Dose in ASICs Using CMOS Processes Exhibiting Field-Oxide Leakage

Abstract

We developed a cell-level fault model for logic failure induced in standard-cell ASIC devices exposed to total ionizing dose. This fault model is valid for CMOS process technologies that exhibit field-oxide leakage current under total dose. The fault model was represented at the cell level using hardware descriptive languages (HDL) such as VHDL or Verilog which consequently allowed for cell-level simulation of ASIC devices under total dose using functional simulation tools normally used within the HDL design flow of ASIC devices. We then developed a methodology to identify worst-case test vectors (WCTV) using commercially available automatic test pattern generation (ATPG) tools targeting the developed fault model. Finally, we experimentally validated the significance of using WCTV in total-dose testing of CMOS ASIC devices.