Performance-binning and yield-improvement by clock-edge adjusted circuit for multi-Vdd multi-Vth designed chips

Abstract

The low-power chips are occurring test challenges on chip’s shmoo test on yield and performance degradation. A method for improving the performance-yield from adjusting the clock edge is presented. This work proposes a clock-edge adjusted circuit (CAC) to adjust the duty-cycle for testing multi-Vdd and multi-Vth circuits. Instead of adopting a phase-lock-loop to generate a clock with different frequencies, by external ATE cannot adjust chip-internal clock-frequency after a chip is manufactured. However, by using the proposed CAC circuit, the chip duty cycle can be trimmed. The proposed CAC generates an adjustable wide-range trigger-edge signal for the DUT chip, the duty cycles of the clock with a fixed frequency are adjusted to emulate a fast/slow chip-clock frequency. CAC can quickly push the circuit toward correct functional operation under at-speed shmoo-binning operations. It is an efficient with low-area overhead design-for–test circuit to support multi-Vdd/Vth complex designed chips. The CAC technique jointed with using Agilent-93000 automatic-test-equipment (ATE) is used to validate a four multi-Vdd/Vth Cortex-M0 processors chip. The measurements demonstrate yield improvement and accurate performance evaluation from using the CAC by ATE.