Depletion-mode Thin-film Transistors Research Articles

Low Power Emission Pulse Generation Circuit Based on n-Type Amorphous In-Ga-Zn-Oxide Transistors for Active-Matrix Organic Light-Emitting Diode Displays.

This paper presents a low power emission (EM) pulse generation circuit using n-type amorphous In-Ga-Zn-Oxide (a-IGZO) semiconductor thin-film transistors (TFTs). The low power consumption is achieved by avoiding the shoot-through current paths through an optimized inverter circuit. The proposed circuit consists of 12 TFTs and 2 capacitors including 6 TFTs and 1 capacitor for the inverter circuit to control the pulling-down TFTs. In addition, the wider variance range of the threshold voltage (Vth) from -4 V to 2.5 V is covered by additional 6 TFTs for series-connected two transistor (STT) schemes and two low supply voltages to take into account the negative Vth of depletion-mode TFTs. The simulation of 30 EM circuits is conducted over a 6.1-inch active-matrix organic light-emitting diode display of 120 Hz refresh rate and 3840 × 2160 (UHD) resolution. The power consumption of the EM circuit with the proposed inverter is measured at the low values from 0.836 mW to 0.568 mW over pulse widths from 3 to 2157 horizontal times. It is ensured that the proposed circuit achieves the low power consumption regardless of pulse widths.

Effect of Large-Area Exfoliation and Etching on the Electrical Behavior of Transition-Metal Dichalcogenide Field-Effect Transistors

Large-area layer transfer was used to fabricate multilayer transition-metal dichalcogenide (TMDC) thin-film transistor (TFT) arrays with areas of (40 × 40 μm2) from single-crystal flakes. The effects of plasma etching of the TFT backchannel surface and bulk defects in the layers on the electrical performance and stability of the n-channel depletion-mode TFTs were investigated. Few-layer structures (∼3 monolayers) were fabricated using a dry etching process to thin multilayer (∼60–90 nm thick) TMDC structures. The etching improved the threshold voltage of the TFTs, resulting in a positive threshold voltage shift of +40 V after etching the backchannel, correlating to a bulk trap density of approximately 1 × 1016 cm–3 eV–1 per monolayer. Etching the MoS2 surface resulted in a threshold voltage shift of 0.2 V per nanometer of MoS2 removed (for MoS2 thicknesses >15 nm). For MoS2 layers etched to <15 nm, the threshold voltage changed to ∼1.8 V per nanometer. An observed degradation of the carrier transport and electrical stability of these samples were found to be due to the proximity of the etched surface approaching the active channel region of the device. The results reveal the performance trade-offs of fabricating large-area arrays of few-layer TMDC TFTs using a mechanical exfoliation and dry etching approach.

Gate Driver Circuit Based on Depletion-Mode Indium-Gallium-Zinc Oxide Thin-Film Transistors Using Capacitive Coupling Effect

This article proposes a highly reliable gate driver circuit based on amorphous indium–gallium–zinc oxide (a-IGZO) thin-film transistors (TFTs). The proposed circuit adopted an additional boosted-down structure to maintain the control node (Q-node) of the output TFTs at a low voltage level using the capacitive coupling effect instead of the TFT structure. Consequently, the proposed circuit exhibited stable operation for depletion-mode TFTs with a threshold voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {TH}}$ </tex-math></inline-formula> ) of −3 V. The boosted-down structure improved the operation reliability because it reduced the current flow from Q-node to low-level voltage node by removing the continuously degraded TFTs. The drain–source voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {DS}}$ </tex-math></inline-formula> ) stress on the TFTs connected to the Q-node was reduced by separating these TFTs from the Q-node during bootstrapping. The <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {DS}}$ </tex-math></inline-formula> value during Q-node bootstrapping was reduced from 44.3 to 27.3 V. A pull-down TFT was designed to operate with a 50% duty ratio to ensure reliability against the bias stress. The output node was discharged by the Q-node discharging TFTs in the next stage during the remaining 50% period. Therefore, the output node was discharged with a total duty ratio of 100%. The proposed circuit operated stably as a shift register with <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {TH}}$ </tex-math></inline-formula> varying from −3 to 9 V. Consequently, using capacitive coupling effect, the proposed circuit exhibited reliable operation with depletion- and enhancement-mode a-IGZO TFTs.

Novel Adjustable Self-Compensation Flipped Voltage Follower of ZnO TFTs for Transparent Pixel Circuits

A new flipped voltage follower (FVF) whose current source is realized by a depletion-mode thin-film transistor is proposed. It is successfully applied to a static voltage-programmed pixel circuit. The new FVF has good adjustable self-compensation (ASC) ability, which makes the pixel circuit can compensate for different threshold-voltage shifts of thin-film transistors in not only the driving but also the FVF circuits. The simulation results show that the proposed pixel circuit exhibits a tiny current variation ranging from 1.69% to 3.80% when “global” transistors shift by ±0.2 V or ±0.3 V. In the experiment, the excellent ASC ability of the new FVF is verified by measuring the voltage transfer curve under ultraviolet exposure. Finally, the proposed pixel circuit exhibits a current variation of 1.4% after a stress time of 40000 s.

Supercritical Ammoniation-Enabled Interfacial Polarization for Function-Mode Transformation and Overall Optimization of Thin-Film Transistors.

Thin-film transistors (TFTs) have drawn widespread applications in the increasingly sophisticated display field. Despite the mature process of fabricating enhancement-mode TFTs, lack of facile methods to realize depletion-mode TFTs restrains the implementation of complementary-type circuits, which in turn leads to relatively high power. Here, the supercritical fluid technique is introduced to elaborately design and tune the interface, providing the opportunity for function-mode transformation of TFTs. By harnessing supercritical-assisted ammoniation (SCA) treatment, interfacial polarization induces negative shift of threshold voltage (from 0.2 to -9.8 V), which allows TFTs to remain normally on-state in the absence of complex capacitor-integrated circuits. This convenient technique, without an additional manufacturing process to achieve function-mode transformation, can thus enable the fabrication of comprehensive-mode TFTs under the same process. Furthermore, comprehensive optimizations in the mobility (increases from 2.08 to 17.12 cm2 V-1 s-1), leakage current (reduces from 1.33 × 10-11 to 2.22 × 10-12 A), hysteresis (reduces from 11.2 to 0.2 V), and on/off current ratio (increases from 9.65 × 104 to 7.98 × 106) are achieved simultaneously. Based on conjoint analysis of electrical and material characterization, a reaction model is established for a clearer understanding of the interfacial polarization process. Overall, this low-temperature SCA treatment offers an environmentally benign strategy to modulate the function mode of electronic devices via interfacial engineering and optimize device performance at the same time, exhibiting promise in promoting the implementation of complementary, low-power circuit.

High-Gain Transparent Inverters Based on Deuterated ZnO TFTs Fabricated by Atomic Layer Deposition

Three types of highly transparent inverter circuits, enhancement/depletion, pseudo-CMOS and feedback structures, are fabricated by using zinc-oxide thin film transistors (TFTs) with deuterium plasma immersion to adjust the threshold voltage of the depletion-mode TFTs. Their DC and AC performance are investigated and compared systematically. Especially, the feedback structure inverters demonstrate a maximum gain of −310V/V at ${V}_{DD} =10$ V, which is the highest DC gain ever to be reported for oxide TFTs. Furthermore, the frequency responses of these three inverter types are examined, showing a maximum AC gain of 210 V/V at a 10 mV amplitude input in the pseudo-CMOS inverters. These high-gain transparent inverters have great potential to be used as the common-source amplifiers in the measurement of photo-stimulated electroencephalogram signals.

Electrode-Adaptive Thin-Film Integrated Logic Circuits

Amorphous oxide-based thin-film logic circuits have been fabricated using only an n-type amorphous silicon–zinc–tin–oxide (a-SZTO) channel layer with different source/drain electrodes. Enhancement-mode thin-film transistors (TFTs) were fabricated with oxide electrodes. Depletion-mode TFTs were fabricated with metal electrode. Work functions were measured by Kelvin probemicroscopy. The barrier heights ( $\Phi _{\textsf {B}}$ ) between the a-SZTO channel layer and the electrode were measured to be 1.831, 2.341, and 2.339 eV for the Ti/Al electrode, Indium–silicon–oxide (ISO) electrode, and indium–tin–oxide (ITO) electrode, respectively. The physicalmechanism on the variation of sheet and contact resistances was investigated using a transmission line method, and the change in the resistances is closely related to $\Phi _{\textsf {B}}$ . Inverters were fabricated, with different $V_{\textsf {TH}}$ values adopted simply by using different contact characteristics between various electrodes and the semiconductor channel. High values of voltage gains in inverters were obtained: 12.33 (ISO) and 11.75 (ITO) at $V_{\textsf {DD}}= 5$ V. Itwas also confirmed that more complicated n-type-based NAND and NOR thin-film circuits, implementedwith different electrodes, functioned as conventional logic circuits. This simple fabrication method of thin-film logic circuits opens the possibility of implementing next-generation stacked integrated circuit technology.

Fluorination-Enabled Monolithic Integration of Enhancement- and Depletion-Mode Indium-Gallium-Zinc Oxide TFTs

Common metal-oxide thin-film transistors (TFTs) are unipolar (n-type) in nature, operating either in the enhancement-mode (EM) or depletion-mode (DM). A simple technology allowing easy monolithic integration of both EM and DM TFTs is desirable for improved performance of a metal-oxide circuit. In this letter, the channel regions of select TFTs in a circuit were fluorinated. These TFTs remained EM when subjected to a heat-treatment in a non-oxidizing atmosphere, while the rest was turned DM. The difference between the threshold voltage of an EM and a DM TFT can be simply and precisely modulated by controlling the heat-treatment temperature and duration. An inverter monolithically constructed of EM and DM indium-gallium-zinc oxide TFTs is presented as a demonstration.

Toward Adequate Operation of Amorphous Oxide Thin-Film Transistors for Low-Concentration Gas Detection.

We suggest the use of a thin-film transistor (TFT) composed of amorphous InGaZnO (a-IGZO) as a channel and a sensing layer for low-concentration NO2 gas detection. Although amorphous oxide layers have a restricted surface area when reacting with NO2 gas, such TFT sensors have incomparable advantages in the aspects of electrical stability, large-scale uniformity, and the possibility of miniaturization. The a-IGZO thin films do not possess typical reactive sites and grain boundaries, so that the variation in drain current of the TFTs strictly originates from oxidation reaction between channel surface and NO2 gas. Especially, the sensing data obtained from the variation rate of drain current makes it possible to monitor efficiently and quickly the variation of the NO2 concentration. Interestingly, we found that enhancement-mode TFT (EM-TFT) allows discrimination of the drain current variation rate at NO2 concentrations ≤10 ppm, whereas a depletion-mode TFT is adequate for discriminating NO2 concentrations ≥10 ppm. This discrepancy is attributed to the ratio of charge carriers contributing to gas capture with respect to total carriers. This capacity for the excellent detection of low-concentration NO2 gas can be realized through (i) three-terminal TFT gas sensors using amorphous oxide, (ii) measurement of the drain current variation rate for high selectivity, and (iii) an EM mode driven by tuning the electrical conductivity of channel layers.

Comprehensive Depletion-Mode Model for TFT Assessment

A comprehensive depletion-mode model is developed to describe depletion-mode thin-film transistor (TFT) behavior [1]. This model is distinctly different than the square-law model, which accurately describes enhancement-mode TFT behavior and establishes the equations normally employed for carrier mobility extraction. In the comprehensive depletion-mode model, bulk mobility (μBULK) and interface mobility (μINT) are distinguished based on the assumption that carrier transport can occur within an accumulation layer and/or within the ‘bulk’ of the channel. In this work, the comprehensive depletion-mode model is used to estimate the mobility of p-channel TFTs and solution-processed n-channel TFTs, and also to estimate the free carrier concentration of within the ‘bulk’ of the channel when a TFT exhibits depletion-mode behavior. Simulation reveals that the estimated interface mobility of a depletion-mode TFT is often overestimated when mobility is improperly extracted using the square-law model. [1] F. Zhou et al., “Mobility assessment of depletion-mode oxide thin-film transistors using the comprehensive depletion-mode model,” ECS Journal of Solid State Science and Technology, 3(9), Q3027-Q3031 (2014)

Improving positive and negative bias illumination stress stability in parylene passivated IGZO transistors

The impact of a parylene top-coating layer on the illumination and bias stress instabilities of indium-gallium-zinc oxide thin-film transistors (TFTs) is presented and discussed. The parylene coating substantially reduces the threshold voltage shift caused by continuous application of a gate bias and light exposure. The operational stability improves by 75%, and the light induced instability is reduced by 35%. The operational stability is quantified by fitting the threshold voltage shift with a stretched exponential model. Storage time as long as 7 months does not cause any measurable degradation on the electrical performance. It is proposed that parylene plays not only the role of an encapsulation layer but also of a defect passivation on the top semiconductor surface. It is also reported that depletion-mode TFTs are less sensitive to light induced instabilities. This is attributed to a defect neutralization process in the presence of free electrons.

1-V Full-Swing Depletion-Load a-In–Ga–Zn–O Inverters for Back-End-of-Line Compatible 3D Integration

To enable monolithic three-dimensional integration of the amorphous In–Ga–Zn–O (a-IGZO) and CMOS technologies, the a-IGZO inverters compatible with the low operating voltage ( $\leqq 1$ V) and process temperature of back-end-of-line CMOS have been investigated. We demonstrated a full-swing depletion-load inverter with a voltage gain up to 24 using a CMOS-compatible operating voltage of 1 V. The drive transistor was realized using a low-voltage enhancement-mode a-IGZO thin-film transistor (TFT) with a steep subthreshold swing of 70 mV/decade and a low threshold voltage of 0.5 V. The load transistor was implemented using a bi-layer a-IGZO channel, where the a-IGZO composition was modulated simply by the oxygen flow rate in a depletion-mode TFT.

Mobility Assessment of Depletion-Mode Oxide Thin-Film Transistors Using the Comprehensive Depletion-Mode Model

In an enhancement-mode, n-channel (p-channel) oxide thin-film transistor (TFT), current arises as a consequence of electron (hole) transport within a narrow accumulation layer. The square-law model accurately describes enhancement-mode TFT behavior and establishes the equations appropriate for carrier mobility extraction. In contrast, in a depletion-mode oxide TFT, carrier transport can occur within an accumulation layer and/or within the ‘bulk’ portion of the channel. The comprehensive depletion-mode model accurately describes depletion-mode TFT behavior and establishes a set of equations, different from those obtained from square-law theory, which can be used for carrier mobility extraction. Simulation reveals that when square-law theory mobility extraction equations are used to assess depletion-mode TFTs, the estimated interface mobility is often overestimated.

Fabrication of ZnO Thin-Film Transistors by Chemical Vapor Deposition Method using Zinc Acetate Solution

Zinc oxide (ZnO) thin-film transistors (TFTs) were fabricated by thermal chemical vapor deposition (CVD) using aqueous solutions of zinc acetate (ZnAc2) dihydrate as a source. The precursor was supplied to the substrate by the nitrogen bubbling method through a plate with numerous orifices in the ZnAc2 solution. The ZnO thin films were grown on silicon substrates in the growth temperature (TG) range from 280 to 700 °C. The growth rate of ZnO thin films were linearly proportional to the growth temperature, which suggested that the growth rate is limited by the decomposition of ZnAc2. Depletion-mode TFTs with the ZnO film grown at TG = 350 °C was found to exhibit a relatively low saturation mobility (µsat). However, µsat increased from 1 to 14 cm2·V-1·s-1 and the operational mode was changed from the depletion mode to the enhancement mode by annealing treatment at 200 °C for 2 h under N2 ambient.

Room Temperature Deposited Enhancement Mode and Depletion Mode Indium Zinc Oxide Thin Film Transistors

Enhancement mode and depletion mode indium zinc oxide (IZO) thin film transistors (TFTs) were fabricated on glass substrates using rf magnetron sputtering deposition at room temperature. Plasma enhanced chemical vapor deposited SiO2 or SiNx was used as the gate insulator. The enhancement mode TFTs showed excellent pitch-off and the threshold voltage was 0.75V. The drain current on-to-off ratio was >106. The maximum field effect mobility in the channel was 308 cm2.V-1.s-1. The depletion mode TFTs had a threshold voltage of -2.5V. The drain current on-to-off ratio was >105. The maximum field effect mobility in the channel was 14.5 cm2.V-1.s-1.

The Effect of Deposition Conditions and Annealing on the Performance of High-Mobility GIZO TFTs

The influence of oxygen content, radio-frequency (rf) sputtering power, and postdeposition annealing on the electrical properties of gallium-indium-zinc oxide (GIZO) thin-film transistors (TFTs) is analyzed. Little to no oxygen content in the sputtering chamber is crucial to obtain high-performance devices, even before annealing. In contrast, a high oxygen content and rf power lead, respectively, to unstable/poor performing and depletion mode TFTs before annealing, and mainly for these nonideal conditions, annealing proves to be effective to improve device performance/stability and to decrease the performance discrepancy among TFTs processed under different oxygen and rf power conditions. Best TFTs present a field-effect mobility of 46 cm 2 /V s, subthreshold swing of 0.26 V/dec, threshold voltage of 0.70 V, and an on/off ratio 10 8 -10 9 . These results are a consequence of the optimized processing and of the usage of proper GIZO target composition, 1:2:1 mol.

Functional Porous Tin Oxide Thin Films Fabricated by Inkjet Printing Process

The highly transparent SnO 2 thin films were deposited through solution-based inkjet printing using a simple precursor solution. We were able to fabricate porous tin oxide thin film that has a thin nanoporous layer on top and a thicker meso- and macroporous layer beneath the top layer. The thin-film transmittance is over 98% in the visible wavelength range. A mechanism based on gas evolution was proposed to explain the formation of porous structure. A depletion-mode thin-film transistor using the porous tin oxide channel layer was fabricated with a field-effect mobility of 3.62 cm 2 /V s.

Depletion-mode TFT made of low-temperature poly-Si

This brief reports the fabrication and characterization of a depletion-mode p-channel low-temperature polycrystalline silicon (poly-Si) thin-film transistor (TFT). The poly-Si channel was significantly doped by B ions to make a hole-accumulation layer at zero gate voltage. The depletion-mode poly-Si TFT is normally ON-state, so that the current can flow from the source to the drain at zero gate voltage. The TFT exhibited a field-effect mobility of 60 cm/sup 2//V/spl middot/s, a threshold voltage of 18 V, an on/of current ratio of 10/sup 6/, and a gate voltage swing of 1.1 V/dec.

Dopant and defect interactions in polycrystalline silicon thin-film transistors

The influence of channel doping on the threshold voltage of polycrystalline silicon thin-film transistors (TFTs) has been investigated using both boron and phosphorus implants. For each dopant type, asymmetric TFT behavior was seen between enhancement and depletion mode TFTs, with the enhancement mode TFTs always showing a greater shift in threshold voltage for a given dose. From a detailed analysis of the boron-doped samples, using a two-dimensional device simulator, it was demonstrated that the results could be best explained in terms of an asymmetric density of states, in which the deep trapping state density in the lower half of the band gap increased with increasing boron concentration, and the effect of the dopant on threshold voltage was itself determined by this local defect concentration.

Channel doping effects in poly-Si thin film transistors

The influence of channel doping on the threshold voltage of poly-Si thin film transistors (TFTs) has been investigated using both boron and phosphorus implants. For each dopant type, asymmetric TFT behaviour was seen between enhancement and depletion mode TFTs, with the enhancement mode TFTs always showing a greater shift in threshold voltage for a given dose. From a detailed analysis of the boron-doped samples, using a two-dimensional device simulator, it was demonstrated that the results could be best explained in terms of a non-symmetric density of states, in which the deep trapping state density in the lower half of the band-gap increased with increasing boron concentration. This is the first reported observation in poly-Si of shallow level dopants also introducing deep levels in the majority carrier half band-gap.