Sigma-delta Analog-to-digital Converter Research Articles

Delta-sigma modulation microphone sensors employing a resonant tunneling diode with a suspended microstrip resonator

Purpose This paper aims to propose and demonstrate novel microphone sensors based on the frequency delta-sigma modulation (FDSM) technique, which replaces the conventional delta-sigma modulator in the delta-sigma analog-to digital converters. A key of the FDSM technology is to use a voltage-controlled oscillator (VCO) for converting an input analog signal to a 1-bit pulse-density modulated digital signal. High-performance sensors can be realized if the VCO is replaced by an oscillator whose oscillation frequency depends on an external physical parameter. Design/methodology/approach Microphone sensors are proposed based on FDSM that uses a suspended microstrip disk resonator, where the backside ground plane is replaced by a thin metal diaphragm. A resonant tunneling diode (RTD) oscillator is also used, as the performance of these sensors significantly depends on the oscillation frequency. To demonstrate the basic operation of the proposal, prototype devices were fabricated with an InGaAs/AlAs RTD. Findings A satisfactory noise shaping property, which is a significant nature of delta-sigma modulation, was demonstrated over three decades for the prototype device. A sound-sensing peak was also clearly observed when applying 1 kHz sound from a speaker. Practical implications High-performance ultrasonic microphone sensors can be realized if the sensors are fabricated by using a thin InP substrate with high-frequency oscillator design. Originality/value In this study, the authors proposed and experimentally demonstrated novel microphone sensors, which are promising as future ultrasonic sensors that have high dynamic range with wide bandwidth.

An On-Chip Binary-Weight Convolution CMOS Image Sensor for Neural Networks

A CMOS image sensor (CIS) that can perform on-chip binary convolution is presented. The CIS can greatly reduce memory usage and computational complexity by directly generating a feature map for a binary neural network. The pixel readout of the CIS is performed in the column-parallel fashion using incremental delta-sigma analog-to-digital converters (ADCs). The CIS operates in two different modes: convolution and normal modes. When the column ADC is working in the convolution mode, it works as a first-order delta-sigma ADC and generates convolved images using a binary kernel. In the normal operation mode, the ADC is switched to a second-order delta-sigma ADC with little hardware modification and used to capture high-quality images. To demonstrate the CIS architecture, a 192 × 128-pixel CIS, which occupies an active die area of 14.44 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , is fabricated in a 0.18 μm standard CMOS process. The performance of the CIS is evaluated through measurements and network simulations. In the normal operation mode, the CIS achieves a read noise of 14.79 e <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-</sup> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rms</sub> and a full-well capacity of 6,420 e <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-</sup> with a resulting dynamic range of 53 dB. The power consumptions of the CIS are 49.2 and 52.5 mW during the normal and convolution modes, respectively.

A high-precision synchronous signal acquisition device.

The synchronous and accurate acquisition of multiple features of states is key to assessing the state of power equipment. The highest recorded accuracy of currently available synchronous signal measuring devices in intelligent substations is the 0.2 class, which cannot satisfy the requirements of power equipment such as voltage and current transformers. The accuracy of measurement of a high-precision sigma-delta analog-to-digital converter (ADC) can reach the 0.05 class, but the phase error among several sigma-delta ADCs is large and dynamic because of inadequate real-time sampling. To solve this problem, this paper proposes a double-trigger-time digital conversion technology for synchronous and accurate measurement among sigma-delta ADCs. The results of tests show that its measurement accuracy can reach the 0.05 class.

A Wide Dynamic Range Neural Data Acquisition System With High-Precision Delta-Sigma ADC and On-Chip EC-PC Spike Processor.

A high-performance, wide dynamic range, fully-integrated neural interface is one key component for many advanced bidirectional neuromodulation technologies. In this paper, to complement the previously proposed frequency-shaping amplifier (FSA) and high-precision electrical microstimulator, we will present a proof-of-concept design of a neural data acquisition (DAQ) system that includes a 15-bit, low-power Delta-Sigma analog-to-digital converter (ADC) and a real-time spike processor based on one exponential component-polynomial component (EC-PC) algorithm. High-precision data conversion with low power consumption and small chip area is achieved by employing several techniques, such as opamp-sharing, multi-bit successive approximation (SAR) quantizer, two-step summation, and ultra-low distortion data weighted averaging (DWA). The on-chip EC-PC engine enables low latency, automatic detection, and extraction of spiking activities, thus supporting closed-loop control, real-time data compression and /or neural information decoding. The prototype chip was fabricated in a 0.13 μm CMOS process and verified in both bench-top and In-Vivo experiments. Bench-top measurement results indicate the designed ADC achieves a peak signal-to-noise and distortion ratio (SNDR) of 91.8dB and a dynamic range of 93.0dB over a 10kHz bandwidth, where the total power consumption of the modulator is only 20 μW at 1.0V supply, corresponding to a figure-of-merit (FOM) of 31.4fJ /conversion-step. In In-Vivo experiments, the proposed DAQ system has been demonstrated to obtain high-quality neural activities from a rat's motor cortex and also greatly reduce recovery time from system saturation due to electrical microstimulation.

Economic Modelling and Implementation of Test Signal Generator for Characterization of Continuous Time Sigma-Delta Analog-to-Digital Converter

Now there is a tremendous growth in the specific applications positively related to wireless communications, which posses the specific requirement for mixed-signal integrated circuits. When these independent circuits are used in the unique design of ADC and DAC practical applications, the considerable complexity of the testing increases. BIST is a precisely conventional technique which typically reduces this considerable complexity and prevents functional dependence on high-cost test equipment ATE. Moreover, in Built-In-self-Test (BIST), the output response analyzer (ORA) is the most significant component of architecture of continuous time (CT) sigma-delta analog-to-digital converter (ADC). There are numerous techniques of ORA used for accurate determining the design parameters like integral non-linearity (INL), differential non-linearity (DNL), signal-to-noise ratio (SNR). In this paper, the prime focus is primarily on the modern CORDIC technique which is used as ORA. For the modelling and accurate simulation of this technique Matlab simulink and CADENCE VIRTUOSO EDA tool environment software are properly implemented. A Coordinate Rotation Digital Computer (CORDIC) reduces the design complexity of the independent circuit. The design of ADC can be improved tremendously by typically using BIST. This paper focuses on the system level modelling of test stimuli generator (TSG) and its simulation for accurate characterization of high-resolution sigma-delta ADC. The successful implementation is carefully tested on Matlab simulink tool environment. The auto-testing external test equipment is required to test the integrated structures. TSG is implemented and it helps in extracting of statics and transmission parameters required for characterization of CT sigma-delta ADC.

Instantaneous Average Prediction of the Currents in a PWM-Controlled Two-Level Converter

In this paper, a new method is applied to predict the average value of the phase currents of a two-level voltage source converter. The method uses a suitable model of the converter, the modulation method, and the measurement. The samples given by the analog-to-digital converter (ADC) are used to predict the time progress of the currents in every switching cycle and then calculate its average. This allows removal of the delay introduced by filtering and avoids aliasing in the measurements. The average prediction is contrasted with the pulsewidth modulation (PWM) synchronous sampling method and the sigma-delta ADC with a moving average filter. Applied to a load observer, the method effectively reduces its estimation error. The findings are verified experimentally.

Design and Analysis of Low Power VCO Enabled Quantizer for CT Sigma Delta ADC

This paper presents design and analysis of low power Voltage Controlled Oscillator (VCO) enabled quantizer in Continuous Time (CT) Sigma Delta Analog to Digital converter (ADC) using 180nm CMOS technology using Cadence Virtuoso Tool. The VCO based quantizer in Σ-Δ ADC includes loop filter, VCO quantizer and 3-bit feedback Digital to Analog Converter (DAC). The basic building block of loop filter is Operational Amplifier (OP-AMP). The two stage OP-AMP designed offers 61.51 dB gain with the unity gain bandwidth of 30.59MHz. The keystone of the ADC is VCO based qauntizer clocked at 27.34MHz, which obtains fourth order noise shaping of its quantization noise. A low power VCO is designed using seven stage ring oscillator and Logic Structure Reduction Flip Flop (LRFF) based D-Flip Flop. The VCO based qauntizer with CT Σ-Δ ADC consumes a power of 2.57 m W with a supply voltage of 1.8V.

A Sigma-Delta ADC for Signal Conditioning IC of Automotive Piezo-Resistive Pressure Sensors with over 80 dB SNR.

This paper presents a second-order discrete-time Sigma-Delta (SD) Analog-to-Digital Converter (ADC) with over 80 dB Signal to Noise Ratio (SNR), which is applied in a signal conditioning IC for automotive piezo-resistive pressure sensors. To reduce the flicker noise of the structure, choppers are used in every stage of the high gain amplifiers. Besides, to reduce the required area and power, only the CIC filter structure is adopted as a decimation filter. This filter has a configurable structure that can be applied to different data rates and input signal bandwidths. The proposed ADC was fabricated and measured in a 0.18-µm CMOS process. Due to the application of only a CIC filter, the total active area of the SD-ADC and reference generator is 0.49 mm2 where the area of the decimation filter is only 0.075 mm2. For the input signal bandwidth of 1.22 kHz, it achieved over 80 dB SNR in a 2.5 MHz sampling frequency while consuming 646 µW power.

Sigma-Delta ADC Topology Implementation Based on Partial Discharge Detection using Rogowski Coil Sensor

Partial discharge (PD) diagnostic on high voltage (HV) power cables is a modern technology in order to investigate the insulation health. The trending technology such as wireless sensor network (WSN) and internet of thing (IoT) are mostly process in digital signal by microprocessor where looking toward on automatic system. The high performance of analog to digital converter (ADC) in term of sampling rate which is much expensive in order to convert the high frequency of analog PD signal that captured by Rogowski coil (RC) sensor. Thus, this paper propose the implementation of the Sigma-Delta (∑Δ) ADC topology in Altera DE0-Nano development board as an effective method in this work to replace the conventional ADC chip and the cost is minimal. Then, peak PD detection technique is applied after the conversion of the digital PD signal. The Verilog hardware description language (VHDL) is used in Quartus II software which corporate with Altera DE0-nano development board for the prototype development. In order to achieve the accurate digital sampling of high frequency PD signal, the N-bit of voltage resolution is paramount.

A High-Resolution 2-GHz Fractional-N PLL With Crystal Oscillator PVT-Insensitive Feedback Control

This letter presents a 2-GHz fractional-N phase-locked loop (PLL) with a high-precision delta–sigma digital-to-analog converter (DAC) to overcome the frequency deviation of a crystal oscillator due to manufacturing process, supply voltage, and temperature (PVT). The delta–sigma DAC with high power efficiency and linearity consists of a second-order delta–sigma modulator, a finite impulse response filter, and a low-pass filter. With the proposed PLL architecture, the frequency resolution can be lower than a few thousands of pulse per minute. The PLL is implemented in a 0.13- $\mu \text{m}$ 1P6M CMOS process. With temperature from −40 °C to 80 °C, the measured results of 15 chips show that the frequency deviation of output frequency in PVT decreases from 1 to 0.002 ppm. The phase noise of PLLs is less than −126 dBc/Hz at 1-MHz offset at a carrier frequency of 1.99 GHz. The rms period jitter is below 1 ps at 1.99 GHz, while consuming a total power of no more than 10 mW.

Jitter Sensitivity Analysis of the Superconducting Josephson Arbitrary Waveform Synthesizer.

We present the first jitter sensitivity analysis of a superconducting voltage reference waveform synthesizer with fundamentally accurate output pulses. Successful deployment of a reference waveform source at microwave frequencies will represent a new paradigm for radio frequency metrology. The programmable waveform synthesizer considered in this paper contains a 1.5 bit delta-sigma digital-to-analog converter (DAC) with a sampling frequency of 28 GHz. We quantify the impact of random and deterministic output pulse position jitter (PPJ) on: 1) the amplitude accuracy of the output fundamental tone and 2) the in-band signal-to-noise and distortion ratio (SNDR). The superconducting DAC features a complete lack of output pulsewidth jitter, and random PPJ up to 200 fs rms has a negligible impact on accuracy and SNDR for synthesized tones up to 1 GHz. However, application of nonzero dc bias current is shown to produce deterministic PPJ of up to 5 ps, which, in turn, is shown to degrade the in-band SNDR by 30 dB at 1 GHz unless eliminated with techniques discussed in this paper. We verify the predicted effects of random and deterministic PPJ with simulations in the range of 100 kHz-1 GHz and with experiments in the range of 100 kHz-3 MHz.

A simple circuit technique to relax the feedback timing of ΔΣ ADC for high-speed and high-accuracy applications

A novel and simple circuit technique to relax the feedback timing of input feed-forward ΔΣ analog-to-digital converter (ADC) is proposed for wideband and high-accuracy applications. The proposed method allows the use of low-speed comparator and DEM logic even for high-speed operation which helps to reduce the power consumption. A delta-sigma ADC with relaxed feedback timing was designed and simulated. The results verify the advantages of the proposed technique.

Introduction to the special issue on “High performance analog circuits and design methodologies”

This special issue of the SPRINGER Journal of Analog Integrated Circuits and Signal Processing includes a special section composed of four papers related to ‘‘High performance analog circuits and design methodologies’’. They are selected among those presented at the Joint Conference of 4S-2014/2014 International Conference on Analog VLSI Circuits (AVIC 2014). This conference was jointly organized by Vietnam National University HCMC (VNU-HCM) Integrated Circuit Design Research and Education Center (ICDREC) and Institute of Electrical Engineers of Japan (IEEJ) as an event for commemorating the 20 anniversary of VNU-HCM and 10th anniversary of ICDREC. The conference is the successor of the former International Analog VLSI Workshop. Its purpose is to exchange information, ideas and recent research results on analog VLSI circuits and their applications. The first paper, ‘‘An Improvement of the Current– Voltage Conversion Technique in Over-Current Sensing Circuit for Low-Power Low Dropout Linear Voltage Regulators’’, by Ho Quang Tay, proposes a resistance-less over-current sensing circuit using current–voltage conversion technique for CMOS low dropout linear voltage (LDO) regulators with PMOS as pass device. The second paper, ‘‘Delta-Sigma DAC with Jitter-Shaper-Reducing Jitter Noise’’, by Yuki Watanabe et al., describes a novel delta-sigma digital-to-analog converter (DSDAC) using a jitter shaper to augment the noise caused by clock jitter. The third paper, ‘‘Design of a Symmetry-type Floating Impedance Scaling Circuits for a Fully Differential Filter’’, by Fujihiko Matsumoto et al., proposes the impedance scaling techniques in order to realize a small-size low frequency active filter. The final paper, ‘‘A Low-Power and Low-Gm Linear Transconductor Utilizing Control of a Threshold Voltage’’, by Takeshi Ohbuchi et al., proposes a linear transconductor that is realized by the scheme that the threshold voltages of the transistors are changed by the attenuated input voltage using body effect and reverse short-channel effect. On behalf of the editorial committee of this special section, we would like to express our great thanks to all the authors of the submitted manuscripts and all the reviewers for their great contribution and helpful effort. We also would like to thank all of the committee members for their valuable effort expended in this editorial work. Finally, we would like to express our special thanks to the Guest Editorial Secretary, Professor Cosy Muto, Nagasaki University and Professor Hiroo Sekiya, Chiba University, and the Advisor, Professor Takeshi Shima, Kanagawa University, for all their contributions and efforts.

Delta–sigma DAC with jitter-shaper-reducing jitter noise

We present a novel delta---sigma digital-to-analog converter (DSDAC) using a jitter shaper to augment the noise caused by clock jitter. The jitter shaper is designed for a 0.18 µm CMOS and comprises switched capacitor and sample-and-hold circuits. We simulate the DSDAC in MATLAB and design and simulate the complete jitter shaper circuit in SPICE. We predict that the jitter shaper will improve the signal-to-noise ratio by 47.2 dB (MATLAB) up to 24.6 dB (SPICE).

A Power-Efficient Continuous-Time Incremental Sigma-Delta ADC for Neural Recording Systems

This paper presents an analog-to-digital converter (ADC) dedicated to neural recording systems. By using two continuous-time incremental sigma-delta ADCs in a pipeline configuration, the proposed ADC can achieve high-resolution without sacrificing the conversion rate. This two-step architecture is also power-efficient, as the resolution requirement for the incremental sigma-delta ADC in each step is significantly relaxed. To further enhance the power efficiency, a class-AB output stage and a dynamic summing comparator are used to implement the sigma-delta modulators. A prototype chip, designed and fabricated in a standard 0.18 μm CMOS process, validates the proposed ADC architecture. Measurement results show that the ADC achieves a peak signal-to-noise-plus-distortion ratio of 75.9 dB over a 4 kHz bandwidth; the power consumption is 34.8 μW, which corresponds to a figure-of-merit of 0.85 pJ/conv.

A low-distortion multi-bit sigma–delta ADC with mismatch-shaping DACs for WLAN applications

A low-distortion feed-forward MASH24b-24b sigma–delta analog-to-digital converter (ADC) for wireless local area network (WLAN) applications was presented. The converter exhibits improved performances than the ADCs which have been presented to date by adding a feedback factor in the second stage and employing a 2nd-order noise-shaping dynamic element matching (DEM) scheme. The feedback factor induces a zero in the noise transfer function (NTF) and therefore improves the in-band signal to noise and distortion ratio (SNDR) of the modulator. The mismatch-shaping DEM was introduced and applied to the 4-bit DACs in this paper to improve the resolution and linearity of the ADC. Fabricated in a 0.18μm CMOS process with single 1.8V supply voltage, the converter achieves a peak SNDR of 85.4dB over a 10MHz bandwidth which implies an effective number of bits (ENOB) of 13.90-bit. The spurious free dynamic range (SFDR) is –94dB for a 1.25MHz@–6dBFS input signal at 160MHz sampling frequency. The occupied area is 0.44mm2 and dissipation power 23.4mW.

Data Compression for Image Sensor Arrays Using a 15-bit Two-Step Sigma–Delta ADC

This paper reports a readout integrated circuit with embedded data compression function for image sensors. Data compression is realized by adding a comparator in a two-step incremental sigma-delta analog-to-digital converter (ADC) with a fully floating double sampling integrator. The output difference between two adjacent pixels is compared with a predefined threshold using the comparator to detect redundant pixels. Once the difference is smaller than the threshold, indicating a redundant pixel, the AD conversion is omitted and the redundant information is stored using a Boolean variable. Thus, the conversion speed can be improved and the storage space is saved. An ADC test vehicle with an \(8 \times 8\) array has been fabricated using 0.5-\(\mu \) m CMOS technology. Measurement results show that the frame rate of the image sensor is 10%-236% faster than conventional ADC, and data compression ratios between 1 and 5 are achieved for images with different redundancy. The advantages of this on-chip image compression are the embedded and simple circuits, considerable speed and storage space improvement, and low power consumption. The preliminary results have demonstrated the feasibility and the effectiveness of the proposed compression method.

A Thermometer-Like Mismatch Shaping Technique With Minimum Element Transition Activity for Multibit &lt;inline-formula&gt; &lt;tex-math notation="TeX"&gt;$\Delta\Sigma$&lt;/tex-math&gt;&lt;/inline-formula&gt; DACs

This brief presents a novel mismatch shaping technique for multibit delta-sigma digital-to-analog converters (DACs). It uses the intrinsic quantization noise to randomize the element selection. Different from most existing mismatch shaping techniques that increase the element transition activity, the proposed technique keeps the same transition rate as that for the basic thermometer coding scheme. As a result, it produces much lower intersymbol interference (ISI)-induced distortions. Moreover, it does not produce tones and can high-pass shape the mismatch errors, unlike thermometer coding that produces large distortions due to static mismatch. An efficient hardware implementation based on the vector-quantizer mismatch shaping framework is also presented. Simulations show that the proposed technique can significantly improve DAC linearity in the presence of both ISI and mismatch errors.

A single die 1.2 V 55 to 95 dB DR delta sigma ADC with configurable modulator and OSR

A single die 1.2 V multi-stage noise shaping (Mash) 2-2 delta sigma analog to digital converter (ADC) for wide applications is implemented. The configurable Mash 2-2 modulator with a new decimation filter design is presented to achieve wide and high dynamic range (DR) for multiple practical applications. The novel modulator can be configured as a Mash 2-2 modulator for high precision or a 2-order modulator for low DR. The decimation filter is designed to select the OSR flexibly among cascaded integrator comb (CIC) filter and two half-band filters (HBF). The serial peripheral interface (SPI) can be used to adjust the sampling frequency and the oversampling ratio (OSR). The design was fabricated in a 0.13 μm CMOS process with an area of 0.91 mm2 and a total power of 5.2 mW. The measurement results show that the dynamic range (DR) of the proposed ADC can change from 55 to 95 dB with the configurable OSR from 16 to 256. The spurious free dynamic range (SFDR) and signal-to-noise distortion ratio (SNDR) can get 99 dB and 86.5 dB, respectively.

High Performance Analysis of CDS Delta-Sigma ADC in 45-Nanometer Regime

In this paper, a correlated double sampling (CDS) technique is proposed in the design of a delta sigma analog-to-digital converter (ADC). These CDS techniques are very effective for the compensation of the nonidealities in switched-capacitor (SC) circuits, such as charge injection, clock feed-through, operational amplifier (op-amp) input-referred offset and finite op-amp gain. An improved compensation scheme is proposed to attain continuous compensation of clock feed-through and offset in SC integrators. Both high-speed and low-power operation is achieved without compromising the accuracy requirement. Also this CDS delta sigma ADC is the most promising circuit for analog to digital converter because this circuit reduces noise due to drift and low frequency noise such as flicker noise and offset voltage and also boosts the gain performance of the amplifier. Further, the simulation results of this circuit are verified on using a "cadence virtuoso tool" using spectre at 45 nm technology with supply voltage 0.7 V.