Data Compression for Image Sensor Arrays Using a 15-bit Two-Step Sigma–Delta ADC

Abstract

This paper reports a readout integrated circuit with embedded data compression function for image sensors. Data compression is realized by adding a comparator in a two-step incremental sigma-delta analog-to-digital converter (ADC) with a fully floating double sampling integrator. The output difference between two adjacent pixels is compared with a predefined threshold using the comparator to detect redundant pixels. Once the difference is smaller than the threshold, indicating a redundant pixel, the AD conversion is omitted and the redundant information is stored using a Boolean variable. Thus, the conversion speed can be improved and the storage space is saved. An ADC test vehicle with an \(8 \times 8\) array has been fabricated using 0.5-\(\mu \) m CMOS technology. Measurement results show that the frame rate of the image sensor is 10%-236% faster than conventional ADC, and data compression ratios between 1 and 5 are achieved for images with different redundancy. The advantages of this on-chip image compression are the embedded and simple circuits, considerable speed and storage space improvement, and low power consumption. The preliminary results have demonstrated the feasibility and the effectiveness of the proposed compression method.