The multi-step dynamic reference analog-to-digital converter

Abstract

Abstract The thesis presents the research work on high-speed analog-to-digital converter (ADC), with a design specification of 8 bits of resolution under static operating condition and an effective number of bits (ENOB) of 7 bits at 100 MSample/s. A group of novel Multi-Step Dynamic Reference topologies is proposed in this work, which includes a Two-Step design and a Pipelined one. These converters have built-in digital-to-analog converters (DAC) implemented in the feedforward path to establish the reference voltages dynamically. High-speed conversion is achieved with the same number of comparators as the intended number of bit resolutions. The built-in DACs are realized using simple current steering circuits and R-2R resistor networks. Several techniques such as auto zero, two-step operation, and pipelining are used to achieve the high-speed high-accuracy performance. The Two-Step Dynamic Reference design can achieve a conversion rate of one sample/clock. Compared with the conventional two-step ADC, it does not need to generate residue voltage for the operation of fine stage. The Pipelined design can achieve even higher speed at the expense of more S/H amplifiers and longer latency than the Two-Step one. Residue voltage production is also eliminated, which is a performance limitation in conventional Pipelined ADC. The two proposed topologies use the same basic building blocks. The high-speed comparator is designed using auto-zero technique to realize high accuracy. The effect of channel charge injection is also eliminated by employing proper clock scheme. TheThe thesis presents the research work on high-speed analog-to-digital converter (ADC), with a design specification of 8 bits of resolution under static operating condition and an effective number of bits (ENOB) of 7 bits at 100 MSample/s. A group of novel Multi-Step Dynamic Reference topologies is proposed in this work, which includes a Two-Step design and a Pipelined one. These converters have built-in digital-to-analog converters (DAC) implemented in the feedforward path to establish the reference voltages dynamically. High-speed conversion is achieved with the same number of comparators as the intended number of bit resolutions. The built-in DACs are realized using simple current steering circuits and R-2R resistor networks. Several techniques such as auto zero, two-step operation, and pipelining are used to achieve the high-speed high-accuracy performance. The Two-Step Dynamic Reference design can achieve a conversion rate of one sample/clock. Compared with the conventional two-step ADC, it does not need to generate residue voltage for the operation of fine stage. The Pipelined design can achieve even higher speed at the expense of more S/H amplifiers and longer latency than the Two-Step one. Residue voltage production is also eliminated, which is a performance limitation in conventional Pipelined ADC. The two proposed topologies use the same basic building blocks. The high-speed comparator is designed using auto-zero technique to realize high accuracy. The effect of channel charge injection is also eliminated by employing proper clock scheme. The ii ATTENTION: The Singapore Copyright Act applies to the use of this document. Nanyang Technological University Library