Abstract

This paper presents a second-order discrete-time Sigma-Delta (SD) Analog-to-Digital Converter (ADC) with over 80 dB Signal to Noise Ratio (SNR), which is applied in a signal conditioning IC for automotive piezo-resistive pressure sensors. To reduce the flicker noise of the structure, choppers are used in every stage of the high gain amplifiers. Besides, to reduce the required area and power, only the CIC filter structure is adopted as a decimation filter. This filter has a configurable structure that can be applied to different data rates and input signal bandwidths. The proposed ADC was fabricated and measured in a 0.18-µm CMOS process. Due to the application of only a CIC filter, the total active area of the SD-ADC and reference generator is 0.49 mm2 where the area of the decimation filter is only 0.075 mm2. For the input signal bandwidth of 1.22 kHz, it achieved over 80 dB SNR in a 2.5 MHz sampling frequency while consuming 646 µW power.

Highlights

  • Sensor transducers have been the focus of research for sensor-measuring instruments in automotive and medical systems and have been adopted in pressure transducers and humidity-sensing systems, among others [1,2,3]

  • The choppers clock frequencies are decided in the way that the flicker noise is pushed to the frequencies that are out of the band of interest

  • The structure has been applied in a signal conditioning IC for automotive piezo-resistive pressure sensors

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Summary

Introduction

Sensor transducers have been the focus of research for sensor-measuring instruments in automotive and medical systems and have been adopted in pressure transducers and humidity-sensing systems, among others [1,2,3]. The applied PRT sensor provides a signal with the range of 10–110 mV depending on the pressure amount. Due to the different frequencies of temperature and pressure signals, the signal bandwidth of the ADC, as well as data rate, should be reconfigurable. This paper presents a second order discrete-time Sigma-Delta (SD)-ADC with over 80 dB SNR designed for signal conditioning IC for the automotive piezo-resistive pressure sensors. The main challenge of this work is to keep the area of the SD-ADC below 0.5 mm , while keeping the resolution over 12-bit This structure avoids applying Half-Band (HB) filters in the decimation filter as they are bulky and power-hungry blocks [8,9,10,11].

Architecture of the SDM
The dynamic comparator is
Structure
Configurable Decimation Filter
Results
13. Post-simulation
14. Measurement
15. Measurement results of the the FFT
Conclusions
Full Text
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