Abstract
Bit-serial and bit-parallel arithmetic for parallel realization of CIC (cascaded integrator-comb) filters for decimation in DeltaSigma converters are described. This paper goes forward by realizing a CIC filter, which is designed for use as the first stage of a four-stage decimation filter with down-sampling factor of 128. It is a fifth-order recursive CIC filter which reduces the sampling rate by 16. The CIC filter is realized based on bit-parallel, conventional bit-serial, bit-serial with address decoder, and bit-serial with one-hot pointer architectures. Two halfband filters and one FIR drop correction filter follow the CIC filter each reducing the sampling rate by two. The minimum required stopband attenuation of the decimator is -120 dB and the passband ripple is less than 0.0003 dB. Different realizations of the CIC filter are synthesized on standard-cell library of a 0.18 mum CMOS process. We have concluded that bit-parallel arithmetic is the best implementation considering power consumption compared to the other architectures while conventional bit-serial implementation delivers the lowest area
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