A decimation filter design and implementation for oversampled sigma delta a/d converters

Abstract

The area, speed and power consumption of oversampled data converters were governed largely by decimation filters in sigma delta A/D converters. The paper presented a design and implementation of a low power and high-speed sigma delta digital decimation filter which it was designed by top-down method. The decimation filter consists of a modified cascaded integrator-comb (CIC) decimation filter and two-stage half-band filter. The proposed CIC filter has 15% less hardware and 53% power saving compared to conventional CIC filters. The filter is implemented using 0.6-/spl mu/m CMOS standard cell and contains 6,560 equivalent gates resulting in a power consumption of only 35 mW from a 5-V supply. The decimation filter is very suitable for high-order sigma delta converters.