Gate Delay Research Articles

Fluorescence and Time-Delayed Lasing during Single Laser Pulse Excitation of a Pendant mm-Sized Dye Droplet.

Fluorescence and lasing emission that are produced separately in time during excitation laser pulse for an mm-sized Rhodamine 6G dye-water droplet are reported. The droplet acts as a quasi-spherical closed optical resonator and due to multiple internal reflections, the resonant amplified emission is delayed with respect to fluorescence emission. Measurements of the temporal evolution of the droplet’s emission were performed by varying the signal acquisition gate width and gate delay with respect to the pumping pulse. The droplet emission spectra are structured in two bands which appear one after the other in time: first, the fluorescence emission band which follows pumping laser pulse time shape and then a second band, the lasing band, placed at shorter wavelengths and formed in time after the peak of the pumping laser pulse intensity, on the pulse tail. The lasing threshold pumping intensity is much lower than those for typical dye lasers.

IGBT Series Connection With Soft Switching and Power Recovery in Driver Power Supply

The emergence of applications which require high-voltage switches has created a tendency to use semiconductor device series stacks. These series stacks permit operation at blocking voltages above semiconductor elements’ nominal voltage. Insulated-gate bipolar transistors (IGBT) are currently utilized for controllability and switching speed, when these topologies are employed. The main challenge therewith is guaranteeing voltage balance between IGBTs, both when blocked and when switching transistors. Most of the methods which have been proposed to mitigate static and dynamic voltage unbalances increase transistor losses. The series stack loss-less high voltage switch (LHVS) which mitigates voltage unbalances, thus reducing switching losses, is presented in this paper. LHVS consists of a circuit, which ensures soft IGBT switching, an energy recovery circuit, and a gate delay compensation circuit. Additionally, the insulation voltage level is guaranteed to be equal between control circuit and high-voltage side of each IGBT. The operating principle of the LHVS is detailed in this paper, as is experimental validation which has been performed for three series stack modules. Static unbalances are reduced to 1%, while the differences between collector–emitter voltage curves in switching “ on ” do not surpass 8 ns, and switching losses are reduced by 41%, as compared to the hard-switching topology.

High Performance of Wallace Tree Multiplier Stacking Circuit

In this paper one novel double counter proposed which is quick when contrasted with another normal's parallel counters. First, we are designing binary counter using solely full adders, and after with new symmetric stacking method. We are evaluating these two techniques and displaying how the symmetric stacking method is decreasing the x-or gate delays in the essential route of the binary counter. This kind of our proposed counter is very useful in the existing counter based totally Wallace tree multiplier design. With this new symmetry stacking counter we are lowering delay and increasing the performance of multipliers in VLSI circuits. We are designing and simulating our proposed quick binary counter using Xilinx ISE layout suite14.7.

Temperature switch and router of two and three-mode noise correlation in Pr3+:YSO crystal

Rare earth doped crystal Pr3+:Y2SiO5 has unique features, whose nonlinear response is dynamically triggered and modulated by the interaction between dressing and phonon effect. In this article, we have demonstrated the switching from two-mode bunching to anti-bunching like phenomenon of noise intensity fluctuations used for noise correlation. Here, switching in bunching phenomenon is caused by relative nonlinear phase, which is induced by self- and cross-phase modulation. In contrast with two-mode bunching, three-mode bunching case hardly follows the switching mechanism attributed to the destructive interaction among the phases of Stokes, anti-Stokes and FL signals. We also have realized switching and routing application in two and three mode bunching. Both functions (switching and routing) are controlled by manipulating temperature of cryostat and gate delay. Our experimental results provide the novel technique for switching and channel equalization ratio of about 96%. The intensity switching speed is achieved about 17 ns.

Effect of Various Geometry Parameters on the Performance of Nanoplate Field Effect Transistor with Negative Capacitance.

In this paper, we investigate the impact of geometry parameters such as ferroelectric layer thickness (TFE), extension length (LExt), overlap length (Lov) on negative capacitance FET (NCFET). The NCFET is designed using HfZrO₂ (HZO) ferroelectric materials and the Nanoplate FET (NPFET) presented as a next generation device. We use the 3-D TCAD Sentaurus simulator to analyze characteristics of the NCFET. The NCFET designed considering the stable condition overcomes the Boltzmann limit (i.e., the physical limit in the S.S., which is 60 mV/decade at 300 K) through the steep subthreshold swing (S.S.) and exhibits negative Drain-induced barrier lowering (DIBL) phenomenon. When examining the characteristics of NPFET and NCFET according to LExt and Lov, the NCFET exhibits gate capacitance (Cgg) tendency opposite to that of the NPFET. The NCFET with the scaled VDD has a significant advantage over the gate delay (τd). The NCFET has better performance in environments where conventional device is more vulnerable to short channel effects (SCEs).

Active Gate Delay Time Control of Si/SiC Hybrid Switch for Junction Temperature Balance Over a Wide Power Range

The optimal gate delay time control between the two internal devices to achieve excellent electrical and thermal performance of the Si/SiC hybrid switch is considerably affected by several factors and requires careful adjustment to suit the different operation conditions of power converters. However, the conventional gate control solution for the hybrid switch applies a fixed delay time to achieve the minimum switching loss at a specific load current, resulting in disparities in junction temperature of internal devices over a wide load range. This effectively reduces the safe operating area by risking one internal switch subjected to overrated junction temperature in a wide range operation with regard to power handling condition. To avoid such a serious risk of reliability degradation or thermal breakdown, a novel active gate delay time control strategy based on the electro-thermal coupling loss model is proposed. The gate delay time was dynamically adjusted and optimized according to the operation conditions of power converters so that the operation junction temperature difference of the two internal devices can be minimized. Experimental results demonstrate that the junction temperature of the hybrid switch decreases by 20 °C at 8-kW load condition and its maximum power handling capability increases by 18%, without compromising the power converter's efficiency in a 20 kHz Si/SiC hybrid switch-based dc/dc buck converter compared with the conventional approach.

Ballistic Quantum Transport of Sub‐10 nm 2D Sb2Te2Se Transistors

Abstract2D materials, due to their ultrathin dangling‐bond‐free configuration and excellent electrostatic control, have potential as possible Si‐alternative building blocks for future competitive devices. Exploring 2D electronic materials with suitable band gap and high mobility is key to designing ultra‐scaled devices. The electronic properties and device performance of sub‐10 nm 2D Sb2Te2Se are studied by ab initio quantum‐transport simulations. The results show that 2D Sb2Te2Se, a stable system, possesses an indirect bandgap of 1.01 eV and high electron mobility exceeding 103 cm2 V−1 s−1. Through comparing with the ballistic quantum transports of Sb2Te2Se, the n‐metal‐oxide‐semiconductor field‐effect transistor (MOSFET) exhibits better device performance than p‐MOSFET. In particular, not only can the on‐current of n‐MOSFET with gate length Lg = 9 nm reach as high as 1660 µA µm−1, but its other figures of merit including gate capacity (0.72 fF µm−1), delay time (0.31 ps), and power dissipation (0.37 fJ µm−1) also satisfy the International Technology Roadmap for Semiconductors 2020 requirements. Therefore, 2D Sb2Te2Se could become a potential electronic material for next‐generation nanodevices.

Peak minimisation based gate delay compensation for active current balancing of parallel IGBT system

The non-uniform current sharing among the paralleled devices is consequential due to non-identical layout and alteration in parameters of the system consists of power semiconductor devices and gate drivers. The persistent non-uniform current among the paralleled devices arise the various concerns such as de-rating, uneven losses, and heat consequently can lead to reliability and failure issues of the system. This paper presents a simple yet intelligent and effective automatic control for gate delay compensation to achieve active current balancing through current peak minimisation. The current peak minimisation control approach can serve the purpose of minimising system de-rating as well as obtaining nearly uniform dynamic current sharing. The four parallel connected discrete IGBT system is used for experimental validation under unbalanced operating condition. Moreover, the current peak minimization trend evaluation is introduced for gate delay compensation.

Optimizing (HC)$^2$ LC, A Robust Clock Distribution Network For SFQ Circuits

As the world collects more data, the electronics industry is demanding faster and more energy efficient supercomputers, but this is becoming an increasingly challenging goal as Moore's law nears its end. Superconducting electronics, and single flux quantum (SFQ) in particular, is a promising option for future exascale supercomputing. Nevertheless, timing uncertainty-represented by the inaccuracy of gates delays-renders the design of high-frequency clock distribution networks (CDN) to be one of the challenges that is impeding SFQ processors from attaining their full promised potential. As a radical solution to this challenge, the hierarchical chains of homogeneous clover-leaves clocking, (HC) 2 LC, was proposed. (HC) 2 LC uses an asynchronous CDN to provide the timing of a fully synchronous system, promising superior robustness over the conventional zero-skew clock trees with modest area and performance overheads. In this article, we propose algorithms that optimize the construction of the (HC) 2 LC network. We optimize both the insertion delay and the gates-assignment problem resulting in area reduction of 51%, and yield improvement of 166% compared to the unoptimized (HC) 2 LC. Moreover, we propose a placement-aware variation model, and we present a tool, the qHC 2 LC, using both of which, we perform a complete comparison between zero-skew clock trees and (HC) 2 LC. Our simulations show that averaging over the ISCAS'85 benchmark circuits, at the same speed, and with an area overhead of 9%, (HC) 2 LC achieves 52% and 211% yield improvement over zero-skew trees at low and medium ranges of σ of gate delays, respectively.

Analysis Of Toll Gate Traffic Delay Time Using E-Toll System On Waru-Juanda Toll Road

Currently the traffic on the highway is getting crowded, because it filled with so many four-wheeled vehicles. To reduce congestion at the highway then be made to the motorway. But the government's efforts to maximize the use of toll roads to minimize congestion in fact, has not run optimally for payments using the system to pay cash (cash) is less effective. In 2017 PT. Margatama image Surabaya implement E-Toll at the toll booth Waru - Juanda. To find out how the effectiveness of the use of E-Toll system was conducted research to analyze traffic toll gate delay time with the e-toll system on toll roads hibiscus - juanda. Collecting data in this study conducted on Friday at 4:00 p.m. to 20:00 pm and is located at the toll gate Menanggal. The variables used were manual payment system / cash and payment systems using E-toll by noting the number of vehicles entering the toll gate along with the time needed to conduct transactions at toll booths. From the research conducted, the average time delay that is required at the time for using the E-Toll Card was 13.6 seconds / transaction so that they result in queues at toll gates. From these results it can be concluded that the use of E-Toll card is still not effective in reducing congestion at toll booths. The average time delay that is required at the time for using the E-Toll Card was 13.6 seconds / transaction so that they result in queues at toll gates. From these results it can be concluded that the use of E-Toll card is still not effective in reducing congestion at toll booths. The average time delay that is required at the time for using the E-Toll Card was 13.6 seconds / transaction so that they result in queues at toll gates. From these results it can be concluded that the use of E-Toll card is still not effective in reducing congestion at toll booths.

Static and Dynamic Response Comparison of Printed, Single- and Dual-Gate 3-D Complementary Organic TFT Inverters

A dual-gate configuration has been introduced to organic thin-film transistors (TFTs) for full-depletion behavior to enhance the transconductance, subthreshold slope, and drain current on–off ratio. In this letter, we show how those dual-gate effects influence the static and dynamic responses of three-dimensional (3-D) complementary organic logic gates in comparison to their single-gate counterpart. For the comparative study, 3-D inverters and ring oscillators were fabricated by printing directly on plastic foil in both single- and dual-gate configurations. In the static inverter operation, the fully depleted characteristics of the dual-gate TFTs lead to an increase in voltage gain and a dramatic decrease in standby power consumption. In the dynamic ring oscillator operation, the two configurations have comparable gate delays because the use of an additional gate increases not only the drain current but also the load input gate capacitance. Our findings demonstrate the performance of an inverter that can represent the overall operation of complementary logic gates consisting of pull-up and pull-down networks, thereby providing significant insight into the printed organic TFT circuit design using dual gating effects.

Process variation-aware gate sizing with fuzzy geometric programming

Limitations of manufacturing process in nanometer dimensions have led to large discrepancies between the circuit design and the manufactured chip known as process variation. In this paper, a new gate sizing method based on fuzzy geometric optimization approach is introduced for power minimization of digital circuits subjected to timing constraints under process variations. In the proposed geometric optimization approach, an accurate gate delay model is applied in which the delay variation is represented by fuzzy numbers; therefore, the subsequent optimization problem is a fuzzy geometric programing problem. In order to efficiently solve the fuzzy geometric programing problem, firstly, the problem is converted into a fuzzy linear programming problem and then, using the expected value and Mellin transform, it is converted into a non-fuzzy problem which is solved by traditional solution techniques. Experimental results show that, the proposed technique achieve more power reduction compared to a fuzzy linear programming method.

An ICCD camera-based time-domain ultrasound-switchable fluorescence imaging system

Fluorescence imaging in centimeter-deep tissues with high resolution is highly desirable for many biomedical applications. Recently, we have developed a new imaging modality, ultrasound-switchable fluorescence (USF) imaging, for achieving this goal. In our previous work, we successfully achieved USF imaging with several types of USF contrast agents and imaging systems. In this study, we introduced a new USF imaging system: an intensified charge-coupled device (ICCD) camera-based, time-domain USF imaging system. We demonstrated the principle of time-domain USF imaging by using two USF contrast agents. With a series of USF imaging experiments, we demonstrated the tradeoffs among different experimental parameters (i.e., data acquisition time, including CCD camera recording time and intensifier gate delay; focused ultrasound (FU) power; and imaging depth) and the image qualities (i.e., signal-to-noise ratio, spatial resolution, and temporal resolution). In this study, we also discussed several imaging strategies for achieving a high-quality USF image via this time-domain system.

Impact of Interconnect Spacing on Crosstalk for Multi-layered Graphene Nanoribbon

In the recent research world, the overall system performance primarily depends on interconnect delay instead of the gate delay at the nanoscale regime. The impact of spacing between the lines and shrinking technology are rigorously investigated on peak noise and delay under the crosstalk for rough-edged multi-layered graphene nanoribbon (MLGNR) at global lengths. Using a rough-edged MLGNR, a multi-conductor transmission line (MTL) model is accurately demonstrated by considering the effect of coupling capacitance and inter-layer tunnelling conductance. By incorporating lengths and spacing between the coupled MLGNR interconnect, the equivalent electrical model exhibits an insignificant error of 0.91% only. Moreover, the proposed equivalent model is used to demonstrate the delay under the influence of crosstalk and peak noise for coupled interconnect lines. Using industry standard HSPICE, the overall delay and peak noise under the crosstalk are reduced by 45.1% and 9%, respectively at advanced 14 nm technology in comparison to the 32 nm for a fixed layer of rough-edged MLGNR based global VLSI interconnects.

Artificial neural network model for arrival time computation in gate level circuits

ABSTRACT Advances in the VLSI process technology lead to variations in the process parameters. These process variations severely affect the delay computation of a digital circuit. Under such variations, the various delays, i.e. net delay, gate delay, etc., are no longer deterministic. They are random in nature and are assumed to be probabilistic. They keep changing, based on factors such as process, voltage, temperature, and a few others. This calls for efficient tools to perform timing checks on a design. This work presents a technique to compute the arrival time of a digital circuit. The arrival time (AT) is computed using two different timing engines, namely, static timing analysis (STA) and statistical static timing analysis (SSTA). This work also aims to eliminate number of false paths. It uses a fast and efficient filtering method by utilizing ATPG stuck-at faults and path delay faults. ISCAS-89 benchmark circuits are used for implementation. The results obtained using the probabilistic approach are more accurate than the conventional STA. It has been verified with an Artificial Neural Network (ANN) model. The arrival time calculated using SSTA shows 7% improvement over that of STA. The absolute error is reduced twofold in the case of the ANN model for SSTA.

Kinetics Model of Femtosecond Laser Ionization in Nitrogen and Comparison to Experiment.

A zero-dimensional kinetics simulation of femtosecond laser ionization in nitrogen is proposed that includes fast gas heating effects, electron scattering (elastic and inelastic) rate coefficients from BOLSIG+ and photoionization based on filamentation theory. Key rate coefficients possessing significant uncertainty are tuned (within the range of variation found in literature) to reproduce the time-varying signal acquired by a bandpass-filtered photomultiplier tube with good agreement up to several hundred nanoseconds. Separate spectral measurements calibrate the relative strength of signal components. Derived equations relate the model to experimental measurements in absolute units. Reactions contributing to the rate of change of important species are displayed in terms of absolute rate and relative fraction. In general, decreasing the gas density lengthens the duration of early reactions and delays the start of later reactions. The model agrees with data taken in a variable temperature and pressure free jet by an intensified camera. Results demonstrate that initial signal depends primarily on gas density and secondarily on gas temperature. The optimal (maximum) initial signal occurs at a gas density below atmospheric. Decreases in gas density alter the evolution of excited-state populations, postponing the peak (while reducing its value) and slowing the rate of decay. For the optimal case, populations are favorably shifted in time with respect to the gate delay (and width) to boost the signal. Reductions in gas temperature generally enhance initial signal due to elevated dissociative recombination of cluster ions (along with excited-state coupling from quenching and energy pooling).

An advanced spectroscopic approach (LIBS in combination with AAS): a steadfast means to probe the elemental composition of monosodium glutamate

The elemental composition of monosodium glutamate (MSG) was probed by engaging a laser-induced breakdown spectroscopy (LIBS) analytical technique. The LIBS spectra of MSG were acquired in air pressure with an appropriate detector (LIBS2000 + , Ocean Optics) with an optical resolution of ~0.06 nm in the spectral range from 220 to 720 nm. Analyses of the acquired LIBS spectra revealed the presence of Ag, Ca, Mg, S and Na in the sample. To maximize the signal to noise ratio in the resulting LIBS spectra, the experimental parameters, such as pulse energy and gate delay, were optimized. The accomplishment of local thermodynamic equilibrium supposition was confirmed by the McWhirter’s criterion and in view of the relaxation time, as well as the diffusion length of the atoms in the plasma. For the determination of relative concentrations of detected elements in MSG, we used three LIBS-based approaches, i.e. by setting the concentration of Na as the calibration, by setting the sum of all concentrations as the calibration and by the calibration curve method. The same sample was also subjected to the more standard analytical tool of atomic absorption spectroscopy, and its results were cross-compared with the findings of LIBS to confirm its validity. It was highly encouraging to find that both results were in sound agreement.

Process-Induced Power-Performance Variability in Sub-5-nm III–V Tunnel FETs

We examine the power-performance variability of a projected sub-5-nm GaAsSb/InGaAs vertical tunnel FET considering various process control tolerances in the state-of-the-art device integration and propose countermeasures in device design. Nominal and three-sigma-corner device characteristics generated in quantum-mechanical/TCAD simulations are used to calibrate a semiempirical compact model, based on which the nominal and variability-inclusive energy-delay landscapes are extracted from ring-oscillator circuit simulations at sub-500-mV supply voltages. Variations in four parameters are identified as of major impact on the worst-case speed loss and iso-speed energy penalty: dopant pocket thickness, gate work function, hetero-band offset, and body thickness (in descending order). Variability-resilient device options are explored against pocket thickness variation, including: 1) pocket desensitization with increased thickness and reduced doping concentration and 2) broken-gap tunnel FET with a negative effective band gap. Reengineered devices achieve $ speed loss and $ energy penalty for (0.1–1) ns gate delay with respect to the nominal corner.

Mini-Review: Modeling and Performance Analysis of Nanocarbon Interconnects

As the interconnect delay exceeds the gate delay, the integrated circuit (IC) technology has evolved from a transistor-centric era to an interconnect-centric era. Conventional metallic interconnects face several serious challenges in aspects of performance and reliability. To address these issues, nanocarbon materials, including carbon nanotube (CNT) and graphene, have been proposed as promising candidates for interconnect applications. Considering the rapid development of nanocarbon interconnects, this paper is dedicated to providing a mini-review on our previous work and on related research in this field.

Quantitative analysis of Fuller's earth using laser-induced breakdown spectroscopy and inductively coupled plasma/optical emission spectroscopy.

Fuller's earth, most commonly known as Multani Matti (clay) in Urdu, among its various utilizations is traditionally used in skin care cosmetics, particularly for removing blackheads and to treat oily skin. It is also used for improving skin complexion. In this paper, laser-induced breakdown spectroscopy (LIBS) was effectively employed for the quantitative investigation of various clay samples for their special uses. To get the LIBS spectra with an optimal signal-to-noise as well as for a more robust and accurate analytical investigation, different experimental parameters (laser energy, gate delay time, and the distance between target and focusing lens) were optimized before the experiments on actual samples. The analysis of emission spectra revealed the presence of many different elements, including Al, Ca, Fe, Mg, Mn, Na, K, Li, S, Si, and Zn. The electron number density and plasma temperatures were determined using the Stark broadened line profile and Boltzmann plot method, respectively. To determine the relative concentration of observed elements, we used an integrated intensity ratio method, integrated intensity of every line from all elements, and calibration free (CF)-LIBS. The prevailing condition of local thermodynamic equilibrium during the experimental executions was verified with multiple criteria. The spectral lines used in CF-LIBS were characterized for the influence from the self-absorption phenomenon, but the same was found insignificant. The findings of our LIBS system were found to agree excellently with the outcomes of the inductively coupled plasma/optical emission spectroscopy, thereby yielding a high statistical correlation factor and hence enlighten the significance of LIBS as a safe and reliable tool for elemental analysis of clay samples.