Artificial neural network model for arrival time computation in gate level circuits

S R Ramesh,R Jayaparvathy

doi:10.1080/00051144.2019.1631568

Abstract

ABSTRACT Advances in the VLSI process technology lead to variations in the process parameters. These process variations severely affect the delay computation of a digital circuit. Under such variations, the various delays, i.e. net delay, gate delay, etc., are no longer deterministic. They are random in nature and are assumed to be probabilistic. They keep changing, based on factors such as process, voltage, temperature, and a few others. This calls for efficient tools to perform timing checks on a design. This work presents a technique to compute the arrival time of a digital circuit. The arrival time (AT) is computed using two different timing engines, namely, static timing analysis (STA) and statistical static timing analysis (SSTA). This work also aims to eliminate number of false paths. It uses a fast and efficient filtering method by utilizing ATPG stuck-at faults and path delay faults. ISCAS-89 benchmark circuits are used for implementation. The results obtained using the probabilistic approach are more accurate than the conventional STA. It has been verified with an Artificial Neural Network (ANN) model. The arrival time calculated using SSTA shows 7% improvement over that of STA. The absolute error is reduced twofold in the case of the ANN model for SSTA.

Highlights

Semiconductor devices play a very important role in today’s world
It is seen that the values of statistical static timing analysis (SSTA) are lower than the corresponding static timing analysis (STA) values
STA and SSTA arrival times are compared with the Artificial Neural Network (ANN) model

Summary

Introduction

Semiconductor devices play a very important role in today’s world. The interconnects that connect various portions of the circuitry have become a reason for reduction of circuit performance in these devices. Timing analysis plays a crucial role in VLSI chip design. This process helps to analyse whether a chip design meets the timing constraints or not. The gates of the circuit are represented by vertices, and the interconnects or wires between the gates are represented by edges. A timing graph G is a graph with a set of vertices V and set of edges E It is represented as G = {V, E} where V = {v1,v2,v3, .

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Conclusion