A comparison on timing analysis using probabilistic approaches

Abstract

This paper presents a comparison on various timing analysis methods. Timing analysis is a critical step in any digital integrated circuits. Static timing analysis is a method to validate the timing performance of a digital circuit without requiring simulation. Technology and the process scaling to nanometer regime have lead to significant increase in process variations. These variations are needed to incorporate in static timing analysis. In the proposed method the delays of the gates and the arrival time are modeled by probabilistic distributions. The gate delays and the arrival time are modeled by using the operations statistical convolution integration and the statistical maximum. The delay values used is extracted from the standard delay format file for each gate. The method is tested by using various ISCAS benchmark circuits. Further statistical static timing analysis with arrival time at 3σ points away from the mean is calculated. The statistical static timing analysis results are found to be more accurate as it considers process variations.