Critical Paths Selection and Test Cost Reduction Considering Process Variations

Abstract

Current ATPGs rely on timing analysis tools to identify critical paths for generating path-delay fault (PDF) test patterns. However, the model-based conventional static timing analysis (STA) and statistical static timing analysis (SSTA) tools are not capable of considering the actual silicon variations. In this paper, we present a timing analysis technique that improves the analysis of paths delay considering actual silicon variations. This technique models correlations between basic gate types in the standard cell library, paths, and ring oscillators (ROs) considering variations. The post-silicon measurements on the ROs can help predict actual delay distribution. Paths are then ranked and critical path-delay faults are identified accordingly. This technique is more accurate than STA in conventional PDF test flow, and faster and more accurate than SSTA method. The ranking results show that our flow is advantageous to the rankings obtained using STA and SSTA with ≥15% and ≥ 52% test cost (PDF pattern count) reduction, respectively.