Process variation-aware gate sizing with fuzzy geometric programming

Abstract

Limitations of manufacturing process in nanometer dimensions have led to large discrepancies between the circuit design and the manufactured chip known as process variation. In this paper, a new gate sizing method based on fuzzy geometric optimization approach is introduced for power minimization of digital circuits subjected to timing constraints under process variations. In the proposed geometric optimization approach, an accurate gate delay model is applied in which the delay variation is represented by fuzzy numbers; therefore, the subsequent optimization problem is a fuzzy geometric programing problem. In order to efficiently solve the fuzzy geometric programing problem, firstly, the problem is converted into a fuzzy linear programming problem and then, using the expected value and Mellin transform, it is converted into a non-fuzzy problem which is solved by traditional solution techniques. Experimental results show that, the proposed technique achieve more power reduction compared to a fuzzy linear programming method.