Delay-locked Loops Research Articles

A general jitter analysis of DLL considering the jitter accumulation effect of loop capacitor

This paper presents a time-domain model for general jitter analysis of delay-locked loops (DLLs). According to this model, the noise contribution of each part of the circuit is specified at the output of DLL, and a closed-form relationship is extracted. By this closed-form relationship, we show that accumulated jitter, known as jitter peaking, always exists due to the loop filter capacitor in a widely used DLL configuration. The effect of jitter accumulation can cause an unstable lock state. A conventional DLL is simulated in 0.18 µm CMOS technology to verify the closed-form relationship.

Phase Noise Analysis for Stochastically Injected Oscillators

For energy-efficient low-noise clock generation, many multiplying delay-locked loops or injection-locked clock multipliers adopt probabilistic gating to calibrate circuit nonidealities. However, it has not yet been studied how this stochastic behavior affects the phase noise of the clock generator. To answer this question, this brief proposes a novel phase noise analysis methodology for stochastically injected oscillators. Specifically, the power spectral density of a non-wide-sense-stationary process, consisting of multiple cyclostationary processes occurring stochastically, is derived from time-averaged autocorrelation. In order to obtain the required expected value, a Markov-chain-based method to calculate the probability of each state is also presented. For validation, phase noise obtained from the proposed analysis is compared with time-domain simulation results, which demonstrates that the proposed analysis provides accurate estimation.

GNSS position-aided delay-locked loops for accurate urban navigation

GNSS position-aided delay-locked loops for accurate urban navigation

All-digital transmit beamformer for portable high-frequency ultrasound imaging systems.

To meet the requirements of high-frequency ultrasound imaging systems, a transmit-beamforming integrated circuit with higher delay resolution than conventional transmit-beamforming circuits, which are typically implemented using field-programmable gate array chips, is presented. It also requires smaller volumes, allowing for portable applications. Its proposed design includes two all-digital delay-locked loops providing a specified digital control code for a counter-based beamforming delay chain (CBDC) to generate stable and suitable delays for exciting the array transducer elements without variations in process, voltage, and temperature. Moreover, to maintain the duty cycle of long propagation signals, this novel CBDC requires only a few delay cells, significantly reducing hardware costs and power consumption. Simulations were conducted, revealing a maximum time delay of 451.9ns with a time resolution of 652ps and a maximum lateral resolution error of 0.04mm at 6.8mm.

A Broadband Spectrum Channelizer With PWM-LO-Based Sub-Band Gain Control

A broadband spectrum channelizer employing pulsewidth-modulated local-oscillator (PWM-LO)-based sub-band amplitude control is demonstrated. The channelizer has an analog bandwidth of 800 MHz and partitions the input spectrum into eight contiguous sub-bands. The design employs an approach based on frequency folding from harmonics of multi-phase periodic clocks and allows for scaling the relative gain of the sub-bands over a 20-dB range. This relaxes the compression performance of the channelizer baseband and sub-analog-to-digital converter (ADC) dynamic range in the presence of large sub-bands. Gain control on individual sub-bands is performed by employing customized PWM-LO waveforms, where the PWM-LO pulses are generated using delay-locked loops (DLLs). Off-chip learning employing a neural network is used to estimate the PWM symbol pulsewidths required for setting the desired LO harmonic levels. A 1.6-GS/s spectrum channelizer integrated circuit (IC) is implemented in a 65-nm CMOS process to verify the architecture. The measured channelizer gain is 51.6–56.5 dB without gain scaling and provides a range of 37–59 dB with PWM-LO gain control. Gain scaling at a specific harmonic improves blocker compression in an unattenuated sub-band from −34 to −16 dBm. The in-band gain compression with gain scaling also increases from −32 to −17 dBm.

Simulation studies on the transient dose rate effect of analog delay locked loops

This paper presents the transient dose rate (TDR) effect of analog Delay Locked Loops (DLLs). The analog DLL circuits are built upon a previous design, and the typical photocurrents are calculated by the Sentaurus TCAD. Both single double-exponential and dual double-exponential functions are successfully introduced to fit the different photocurrent waveforms with change of the simulated nodes, which then are integrated into the SPICE models for later circuit simulations. Firstly, the radiation effect of individual sub-circuits (e.g. charge pump) and their coupling relationships are analyzed. The simulation results show that the current-charge pump as the most sensitive module can result in the biggest clock error, followed by the voltage-controlled delay line; although the global radiation effect of DLL (use current-charge pump) is almost the same with the individual current-charge pump exposed to the radiation, there are still some coupled relationships exhibiting among modules. Also, the simulation results are qualitatively consistent with previous experiment phenomena; further, it is demonstrated that the voltage-charge pump technique can be used effectively to improve the TDR effect of the charge pump; lastly, the effect of global photocurrents on the rail span collapse is indirectly considered through power analysis. However, it is found that this effect can be negligible due to the very small variation of power.

Online Safety Checking for Delay Locked Loops via Embedded Phase Error Monitor

In today's automotive ICs, online safety checking is often required in order to achieve a high Automotive Safety Integrity Level (ASIL). For a Delay-Locked Loop (DLL), the most important safety (or health) indicator is the “phase error between the input clock signal and the output clock signal”. In this paper, we present a phase error monitoring scheme for DLLs, using circuits made of only standard cells. The proposed scheme can monitor the phase error continuously to record its worst-case values during a designated monitoring session. As a result, hazardous phase error glitches can be exposed and an alarm can be raised. We have implemented this monitoring scheme for a Delay Lock Loop in a 90 nm CMOS process and post-layout simulation is conducted to verify its effectiveness. Experimental results show that it can help expose hazards induced by dynamic power glitches that occurs within 1ns.

20-ps Resolution Clock Distribution Network for a Fast-Timing Single-Photon Detector

The time resolution of active pixel sensors whose timestamp mechanism is based on time-to-digital converters is critically linked to the accuracy in the distribution of the master clock signal that latches the timestamp values across the detector. The clock distribution network (CDN) that delivers the master clock signal must compensate process-voltage-temperature variations to reduce static time errors (skew) and minimize the power supply bounce to prevent dynamic time errors (jitter). To achieve sub-100-ps time resolution within pixel detectors and thus enable a step forward in multiple imaging applications, the network latencies must be adjusted in steps well below that value. Power consumption must be kept as low as possible. In this work, a self-regulated CDN that fulfills these requirements is presented for the FastICpix single-photon detector aiming at a 65-nm process. A 40-MHz master clock is distributed to 64×64 pixels over an area of 2.4×2.4 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> using digital delay-locked loops, achieving clock leaf skew below 20 ps with a power consumption of 26 mW. Guidelines are provided to adapt the system to arbitrary chip area and pixel pitch values, yielding a versatile design with very fine time resolution.

Using D flip-flop with reset terminal to design PFD in QCA nanotechnology

ABSTRACT Quantum-dot cellular automata (QCA), which has very high speed and very low area and power consumption, is one of the proposed nanotechnologies to design digital electronic circuits. Phase-locked loops (PLLs) and delay-locked loops (DLLs) are two important blocks in transceiver circuit design. The phase-frequency detector (PFD), which measures the phase and frequency differences of two signals, is one of the main blocks in PLLs and DLLs architectures. In this paper, two novel phase-frequency detector designs have been proposed in QCA technology using rising and falling edge D flip-flops with reset ability. The proposed PFDs can provide the basis for designing larger circuits such as phase-locked loops and delay-locked loops that are widely used in communication systems. The two proposed structures for the phase-sensitive detector in quantum cellular automata technology, which detect the phase differences of rising and falling edges of their inputs, are composed of 174 and 170 cells, occupying only 0.27 and 0.26 μm2, respectively. Smaller area, better jitter performance, smaller glitch and reset path time, higher operating frequency and lower power consumption are the main advantages of proposed designs in comparison with CMOS PFDs. All the simulations are done by QCADesigner software and QCAPro Software.

A Low-Power Multichannel Time-to-Digital Converter Using All-Digital Nested Delay-Locked Loops With 50-ps Resolution and High Throughput for LiDAR Sensors

This article presents a low-power, all-digital multichannel time-to-digital converter (TDC) for light detection and ranging (LiDAR) sensors. The proposed TDC architecture measures the time interval through a coarse counter, middle, and fine delay line-based interpolation technique (the Nutt method). Automatic calibration by middle and fine all-digital delay-locked loops (ADDLLs) is provided to ensure the stability of the generated time slots. Charge pump, loop filter, and voltage-controlled delay line inside the conventional analog delay-locked loops (DLLs) are replaced by an accumulator (ACC) and digitally controlled delay line (DCDL). This makes the design particularly compact, low power, and suitable for multichannel applications. The presented architecture can generate information for amplitude variation (walk error) compensation. This information is generated by measuring the pulsewidth and position of three successive STOP pulses inside each channel within a single-shot measurement. A low-jitter injection-locked frequency multiplier (ILFM) generates a 625-MHz internal clock signal out of 25-MHz external reference oscillator, which shrinks the number of delay elements to cover one period of the reference clock and improves the precision of the TDC. Operation at higher frequency provides high throughput and short conversion time (less than 3 ns). The three-level TDC offers 13.1- $\mu \text{s}$ maximum input range and 50-ps resolution. The measured DNL and INL of the TDC circuit are 0.47 and 0.71 LSB, respectively. The TDC circuit is implemented in a 180-nm standard CMOS process with a die size of 1.5 mm $\times1.5$ mm. The total power consumption of the multichannel TDC is 87.6 mW.

A 0.2-1.3 ns Range Delay-Control Scheme for a 25 Gb/s Data-Receiver Using a Replica Delay-Line-Based Delay-Locked-Loop in 45-nm CMOS

For delay-regulation purposes, delay-line based applications requiring data to be applied at the input can not use conventional delay-locked-loops (DLLs), which necessitate the reference clock to be applied at the input of the delay-line. This brief presents a DLL which uses a part of the data delay-line, referred to as replica delay-line, to match the delay of the data delay-line to the input clock period. The DLL performs this delay-regulation by setting the current ratio in its charge pump to a particular ratio defined by the delay-elements in the data and the replica delay-line. Designed in 45-nm SOI CMOS, the 4-tapped differential replica delay-line based DLL (R-DLL) is demonstrated to regulate the delay of the tunable data delay-line to within one least significant bit (LSB) delay-lock error for the input clock frequencies ranging from record 0.77-5 GHz. The R-DLL consumes only 17 mW of power and 0.009 mm2 of area, while enabling the 32-tapped 25 Gb/s differential data delay-line to achieve a lock range $2.3\times $ better than reported in literature.

In-sensor time-domain classifiers using pseudo sigmoid activation functions

This work presents an ultra-low-power classifier that can be integrated within energy-constrained bio-sensors to enable rapid analysis for continuous health monitoring. The in-sensor classifier saves significant transmission energy by extracting critical information locally to eliminate the need of transmitting raw data to centralized servers for remote signal processing. The convolutional-neural-network (CNN)-based classifier is built by using reconfigurable delay-locked loops (DLLs) to carry out classification algorithms with time-domain multiply-accumulate (MAC) operations. Pseudo sigmoid activation functions are realized by regenerative comparators that transform weighted timing to probabilities. The presented classifier achieves low-power consumption of 240.34 nW while performing up to 20 k operations per second. The proposed time-domain classifier reduces the energy to 36% of the previous works.

A low-jitter clock multiplier using a simple low-power ECDLL with extra settled delays in VCDL

This paper investigated the improved voltage-controlled delay line (VCDL) suitable for edge-combining delay-locked loops and multiplying delay-locked loops (MDLLs). One of the most important factors in jitter production is to increase the number of delay cells. By generating more delays in each stage of VCDL, further delays with a certain coefficient are produced in each delay cell stage, which are suitable for MDLLs. This can reduce the output jitter and power consumption of the proposed structure. An improved frequency multiplication is used to multiply the generated frequencies, which reduces the occupied area and power consumption in comparison to conventional ECDLL. Since the phase-noise of VCDL is affected by the noise of control voltage, the noise transfer functions of control voltage will be transferred to the ECDLL output. Reducing noise from the delay cell can help reduce the overall system phase noise. Post-layout simulations with TSMC 0.13 μm technology are performed using CMOS technology in the frequency range of 8 MHz to 1 GHz, and the RMS jitter is 1.06 ps at a frequency of 1 GHz. Reduction in the number of delay cells and use of low-power 50% duty cycle corrector can cause low output jitter and reduce power consumption. The overall power consumption of the system is 3.01 mW at a frequency of 1 GHz in the fast-locking situation with 1.2 V power supply, which demonstrates improvement in the results compared to previous related works.

Novel Phase-frequency Detector based on Quantum-dot Cellular Automata Nanotechnology

The electronic industry has grown vastly in recent years, and researchers are trying to minimize circuits delay, occupied area and power consumption as much as possible. In this regard, many technologies have been introduced. Quantum Cellular Automata (QCA) is one of the schemes to design nano-scale digital electronic circuits. This technology has high speed and low power consumption, and occupies very little area. Phase-locked loops (PLLs) and delay-locked loops (DLLs) are blocks that are commonly used in telecommunication applications. One of the most important parts in DLL and PLL is the phase-frequency detector. Therefore, the design of this circuit in QCA technology is of great importance. In this paper, two new phase-frequency detectors sensitive to falling and rising edge have been introduced in QCA technology. Both of the designs are composed of 104 cells; occupy only 0.13 μm2 of an area and 1.5 QCA clock cycles latency. The designs are in one layer and all the inputs and outputs are available to be used by another circuit.

Time-Variant Modeling and Analysis of Multiplying Delay-Locked Loops

This paper presents a novel time-variant model of multiplying delay-locked loops. A simple feed-forward model of the multiplexed ring oscillator mathematically describes the edge realignment process and, by providing an explicit tuning input, allows to be embedded into the time-variant multiplying delay-locked loop model without requiring approximations. Verification of the multiplexed ring oscillator model against detailed circuit simulations is presented. Closed-form expressions for the multiplying delay-locked loop phase noise, as a function of the system parameters and noise sources, are provided.

A Reconfigurable Cross-Connected Wireless-Power Transceiver for Bidirectional Device-to-Device Wireless Charging

This paper presents a reconfigurable cross-connected (CC) wireless power transceiver (TRX) operating at 6.78 MHz and implemented for bidirectional device-to-device (D2D) charging with high efficiency and small system volume. We propose, for the first time, a CC topology applied to a differential class-D power amplifier for significant switching loss reduction. Two delay-locked loops (DLLs) for each power NMOS transistor form the reconfigurable controller, realizing the adaptive deadtime control in the transmitter (TX) mode and the off-delay compensation in the receiver (RX) mode, leading to high power conversion efficiency and safe operation. To realize the inductive load for the TX mode in the whole coupling range at the resonant frequency, we use an on-chip tunable capacitor. Furthermore, we also study the power link efficiency in the D2D direct charging system and verify that the near-maximum power link efficiency can be inherently achieved in this scenario. The proposed wireless power TRX, fabricated in a 0.35- $\mu \text{m}$ CMOS process with 5-V devices, measured a peak D2D total efficiency of 77.2% when the output power is 0.7 W. The maximum charging power is 2.74 W with a total efficiency of 62.7% and the maximum transmission distance is 24 mm, both measured.

Proper Initial Solution to Start Periodic Steady-State-Based Methods

We present a numerical technique that automatically identifies a suitable initial solution to start periodic steady-state methods for simulating non-autonomous circuits at transistor-level. The method avoids the guessing of the initial solution, which may result in divergence of the steady-state method used. For high-Q oscillating circuits, acceleration methods are used to compute the periodic solution. For strongly nonlinear circuits, such as delay-locked loops and switching-mode power supplies, time-domain methods are preferred, e.g., Shooting-Newton. Usually, a number of pre-integration periods is guessed to provide an initial solution for the acceleration method. However, the method may diverge, then the guessing has to be repeated with no clue on the next one. Instead, the technique described here identifies a proper initial solution that makes the method converges, works in the time-domain and makes use of information stored during the integration process, thus is non-invasive for commercial circuit simulators and can be implemented with little effort. Besides, it works in parallel with the integration process, thus computations are cheap to perform. We show experimental results from applying our technique and then start shooting-Newton on five circuits, among which three are industrial and two are strongly nonlinear, that confirm the validity of our mathematical analyses.

Design of High-Order Type-II Delay-Locked Loops With a Fast-Settling-Zero-Overshoot Step Response and Large Jitter-Rejection Capabilities

In this paper, a design method for high-order delay-lock loops (DLLs) is presented and verified through simulations and physical experiments. The general approach is based on selecting the closed-loop transfer function of the DLL, together with identifying the coefficients of the phase-detector and voltage-controlled delay line, and subsequently, solving for parameters of the loop filter of the DLL. Past DLL design approaches relied more on establishing a desired phase margin requirement than attempting to establish a desired input–output behavior. This limited the realization of DLLs to second order; largely a result of the complicated mathematics that arise. As the method proposed in this paper is based on selecting a desired closed-loop transfer function, the issues of stability or phase margin never come to the forefront. This paper will show how a DLL can be designed to achieve a fast-settling-zero-overshoot step response with large jitter-rejection capabilities. The method is simple and easy to execute. No optimization or iteration is necessary. The method is similar to the methods used to design active-RC filter circuits. A fully programmable experimental prototype involving a custom IC implemented in a 130-nm IBM CMOS process was constructed. DLLs with orders ranging from second to eighth will be investigated.

A Wideband Receiver Employing PWM-Based Harmonic Rejection Downconversion

A harmonic rejection (HR) receiver that utilizes discrete-level pulsewidth modulation (PWM) to implement a sinusoidal local oscillator (LO) with intrinsic HR is demonstrated. The PWM-LO is employed in a switching mixer. The receiver can be configured to provide additional HR, by employing multi-phase paths, with appropriate baseband gain coefficients. The PWM generator employs parallel delay-locked loops to implement a three-level natural-sampling dual-edge PWM sinusoidal LO signal, with rejection of the third, fifth, and seventh LO harmonics. Gain control using LO-path pulsewidth control is demonstrated. The design is implemented in a 40-nm CMOS process. The receiver gain with HR is 26.4–30.1 dB in multi-phase LO configuration and 28–31.8 dB in single-phase configuration. The double-sideband noise figure at peak gain is 5.8 dB. The design demonstrates worst case HR3 and HR5 ratios of 47 and 49 dB without calibration for $f_{\mathrm{ LO}}=100$ MHz in the multi-phase configuration, with a total power dissipation of 41.1 mW. With calibration, a single-phase peak harmonic rejection ratio (HRR) higher than 73 dB for the third, fifth, and seventh LO harmonics is demonstrated. Gain dependence of the HRR is studied.

A PVT resilient short-time measurement solution for on-chip testing

As technology continues to shrink, the challenges of developing manufacturing tests for integrated circuits become more difficult to address. To detect parametric faults of new generation of integrated circuits such as 3D ICs, on-chip short-time intervals have to be accurately measured. The accuracy of an on-chip time measurement module is heavily affected by process, supply voltage, and temperature (PVT) variations. This paper presents a new on-chip time measurement scheme where the undesired effects of PVT variations are attenuated significantly. Two Delay Locked Loops (DLLs) are utilized to implement a robust Vernier delay line to measure on-chip time intervals. Measurement results from a fabricated prototype using CMOS 0.18 μm technology indicate that the proposed DLL based TDC reduces the effects of PVT by more than tenfold compared to the conventional on-chip TDC using a Vernier delay line.