A 0.2-1.3 ns Range Delay-Control Scheme for a 25 Gb/s Data-Receiver Using a Replica Delay-Line-Based Delay-Locked-Loop in 45-nm CMOS

Abstract

For delay-regulation purposes, delay-line based applications requiring data to be applied at the input can not use conventional delay-locked-loops (DLLs), which necessitate the reference clock to be applied at the input of the delay-line. This brief presents a DLL which uses a part of the data delay-line, referred to as replica delay-line, to match the delay of the data delay-line to the input clock period. The DLL performs this delay-regulation by setting the current ratio in its charge pump to a particular ratio defined by the delay-elements in the data and the replica delay-line. Designed in 45-nm SOI CMOS, the 4-tapped differential replica delay-line based DLL (R-DLL) is demonstrated to regulate the delay of the tunable data delay-line to within one least significant bit (LSB) delay-lock error for the input clock frequencies ranging from record 0.77-5 GHz. The R-DLL consumes only 17 mW of power and 0.009 mm2 of area, while enabling the 32-tapped 25 Gb/s differential data delay-line to achieve a lock range $2.3\times $ better than reported in literature.