Delay-locked Loops Research Articles

500 kHz – 5 MHz Phase-Locked Loops in High-Temperature Silicon Carbide CMOS

Silicon Carbide (SiC) integrated circuits processes show promise for improved performance in high temperature, high radiation, and other extreme environments. The circuits described are the first implementations of phase-locked or delay-locked loops in SiC. The PLL utilizes a common charge-pump topology including a fully integrated passive loop filter, and were designed with a target maximum operating frequency of 5 MHz. Component blocks use novel topologies to optimize performance in a SiC CMOS process. Experimental results of both the complete PLL as well as the Phase Frequency Detector and Voltage Controlled Oscillator components are presented. Operation of the PLL at frequencies up to 1.5 MHz is demonstrated through test results of unpackaged die.

A New Error Correction Circuit for Delay Locked Loops

A new error correction circuit (ECC) for delay-locked loops (DLLs) using combinational logic and a “peeled” voltage-controlled delay line (VCDL) layout is proposed. The ECC can be used to mitigate missing output pulses due to single-event effects in scaled CMOS processes. The implementation of the ECC results in no significant area penalty or performance degradation of the DLL. Simulations at LETs up to 100 MeV-cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /mg show that the ECC mitigates missing pulses in DLLs fabricated at features sizes down to 40 nm and operating frequencies up to 1 GHz. In addition, any ion strike within the error correction logic components will have no significant impact on the DLL output signal. Emulated results obtained through an FPGA implementation of the ECC demonstrate the effectiveness and portability of the hardening technique.

A new fast‐lock, low‐jitter, and all‐digital frequency synthesizer for DVB‐T receivers

SummaryLock time and convergence time are the most important challenges in delay‐locked loops (DLLs). In this paper we cover French very high frequency band with a novel all‐digital fast‐lock DLL‐based frequency synthesizer. Because this new architecture uses a digital signal processing unit instead of using phase frequency detector, charge pump, and loop filter in conventional DLL, therefore, it shows better jitter performance, lock time, and convergence speed than previous related works. Optimization methods are used to make input and output signals of the proposed DLL in phase. The proposed architecture is designed to cover all channels of French very high frequency band by choosing number of delay cells in signal path. Simulation has been done for 22–27 delay cells, and fREF = 16 MHz, which can produce output frequency in range of 176–216 MHz. Locking time is approximately 0.3 µs, which is equal to five clock cycles of reference clock. All of the simulation results show superiority of the proposed structure. Copyright © 2013 John Wiley &amp; Sons, Ltd.

Analytical Computation of Mean Time to Lose Lock for Langevin Delay-Locked Loops

This paper presents a novel method for the analytical mean time to lose lock (MTLL) computation of coherent second-order Langevin delay-locked loops (DLLs). Analytical MTLL computation is a key task for DLLs, since the computational complexity of numerical MTLL simulations is far too high in many operating ranges of the second-order Langevin DLLs. To obtain the crucial MTLL values analytically without simulations, we rewrite the Langevin stochastic differential equation (SDE) as a vector-valued Ornstein-Uhlenbeck (OU) SDE. It includes a Gaussian noise term, which yields as a solution of the vector-valued OU SDE a time-variant Gaussian distribution. Thus, the complementary error function yields the loss of lock probability and thereby the MTLL. If we replace the complementary error functions by suitable exponential approximations, we obtain a simple MTLL expression with an exponential function as dominant term. The simple exponential MTLL expression yields the optimum loop parameters corresponding to the maximum MTLL. Simulation results confirm that the optimum loop parameters corresponding to our analytical MTLL computation method and to the simplified exponential approximation coincide. Besides the crucial analytical MTLL results, the OU random processes yield additionally the likewise crucial analytical jitter results.

Time-Domain CMOS Temperature Sensors With Dual Delay-Locked Loops for Microprocessor Thermal Monitoring

We report on CMOS temperature sensors that work by measuring temperature-dependent delays in CMOS inverters. Two new features distinguish this work from the prior delay-based temperature sensors. First, our sensor operates with simple, low-cost one-point calibration. Second, it uses delay-locked loops (DLLs) to convert inverter delays to digital temperature outputs: the use of DLLs enables low energy (0.24 μJ/sample) and high bandwidth (5 kilo-samples/s), facilitating fast thermal monitoring. After calibration, measurement errors for 15 chips fabricated in digital CMOS 0.13 μm fall within -4.0~4.0 °C in a temperature range of 0~100 °C, where the temperature chamber used has a control uncertainty of ±1.1 °C. Microprocessor thermal profiling can be a potential application.

20-8 確率ネットワークモデルを用いたNパスマルチパス環境CDMA通信におけるディレイロックループの解析(第20部門無線光伝送)

20-8 確率ネットワークモデルを用いたNパスマルチパス環境CDMA通信におけるディレイロックループの解析(第20部門無線光伝送)

A novel tracking jitter computation method for delay‐locked loops in spread‐spectrum systems

ABSTRACTIn spread‐spectrum navigation systems, the positioning error (or tracking accuracy) is determined from the jitter deviation of delay‐locked loops (DLLs). However, jitter simulations are computationally complex, and conventional analytical methods provide only unsatisfactory and incomplete jitter results. Thus, our contribution presents a novel method for the analytical jitter computation by mapping the stochastic differential equation (SDE) of the DLL onto an Ornstein–Uhlenbeck (OU) SDE. Its solution is the well‐known OU random process, which is a time‐variant Gaussian distribution. The expectation value and the variance of the OU random process yield the jitter deviation. Thus, we derive the analytical time‐variant jitter function with its transient response, which was to date unavailable. Contrary to previous jitter computations based on a loop transfer function, our method covers DLLs of any order. We obtain the loop parameters that minimise the jitter deviation analytically without computationally complex simulations. Above all, our method based on OU random processes enables for the first time an efficient joint analytical mean time to lose lock (MTLL) and jitter computation. Therefore, both computationally complex MTLL and jitter simulations become obsolete for many kinds of DLLs.Copyright © 2012 John Wiley &amp; Sons, Ltd.

A Waveform-Dependent Phase-Noise Analysis for Edge-Combining DLL Frequency Multipliers

Output phase noise for edge-combining delay-locked loops (DLLs) is derived in this study, which is obtained by decomposing the synthesized output waveform into a noise-free signal and a corresponding noise perturbation on it. The noise-free signal, which is affected by the systematic errors as the phase offset between phase detector inputs or delay mismatches among delay cells, possesses a periodic steady-state solution, and therefore leads to output spur. The noise perturbation, on the other hand, will be upconverted to the frequency-multiplied output based on this solution. A general analysis approach is provided that can be applied to the case such as the change of the frequency multiplication factor or the variation of the output duty cycle. The theory is verified by a programmable edge-combining DLL, which has been realized in a CMOS 90-nm technology. The predicted output phase noise has close agreement with simulation results, as well as the measurement data when the frequency multiplication factor changes.

An all-digital DLL using novel harmonic-free and multi-bit SAR techniques

A novel Force/Release technique is proposed to eliminate the harmonic locking issue, which occurs in wide-range operation of Delay Locked Loops (DLLs). The proposed technique does not require replica delay line or multiphase clocks for frequency estimation, and hence, reduces the chip area and power consumption. Moreover, it can be employed, without modifications, to any type of the delay line controller. In addition, an area efficient technique for multi-bit Successive Approximation Register (SAR) DLL is proposed. A complete All-Digital DLL (ADDLL) design implementing the proposed Force/Release technique and the proposed 2-bit SAR scheme is developed. All design units are fully digital, described in Verilog and mapped to silicon using the IBM 0.13μm Artisan standard cell library. The proposed design has an active area of 0.014mm2 and can operate from 110MHz to 1GHz with a fixed latency of one clock cycle. It locks in 12 clock cycles and has a closed loop characteristics.

The TDCpix Readout ASIC: A 75 ps Resolution Timing Front-End for the Gigatrackerof theNA62 Experiment

Abstract NA62 is an experiment under development at the CERN Super Proton Synchrotron, aiming at measuring ultra rare kaon decays. The Gigatracker (GTK) detector shall combine on-beam tracking of individual particles with a time resolution of 150 ps rms. The peak flow of particles crossing the detector modules reaches 1.27 MHz/mm 2 fora total rateof about 0.75 GHz.Ahybrid siliconpixel detectoris beingdevelopedto meet these requirements. The pixel chip for the Gigatracker (TDCpix) is under design. The TDCpix chip will feature 1800 square pixels of 300×300 μm2 arranged in a matrix of 45 rows × 40 columns. Bump-bonded to a silicon pixel sensor it shall perform time stamping of particle hits with a timing accuracybetter than 200 ps rms and a detection efficiencyabove 99%. The chosen architecture provides full separation of the sensitive analog amplifiers of the pixel matrix from the noisy digital circuits of the TDCs and of the readout blocks. Discriminated hit signals from each pixel are transmitted to the end of column region. An array ofTime to Digital Converters (TDC) is implemented at the bottom of the pixel array. The TDCs are based on time tagging the events with the fine time codes generated by Delay Locked Loops (DLL) and have a nominal time bin of ∼100 ps. Time stamps and time-over-threshold are recorded for each discriminated hit and the correction of the discriminator's time-walk is performed off-detector. Data are continuously transmitted on four 2.4 Gb/s serial output links. Adescription of the on-going design of the final TDCpix is given in this paper. Design choices and some technical implementation details are presented. Aprototype ASIC including thekeycomponents of this architecture has been manufactured. The achievement of specification figures such as a time resolution of the processing chain of 75 ps rms as well as charged particle time stampingwitha resolutionbetterthan200psrmswere demonstratedexperimentally.Asummaryoftheseresultsisalso presented in this contribution. The ongoing R&Deffort provided an understanding of some of the processes limiting the timing resolution that can beachievedwithhybridplanarpixels.Some considerationsonthese aspectsare discussedatlast.

Phase Noise Issues With FPGA-Embedded DLLs and PLLs in HEP Applications

Delay Locked Loops (DLLs) and Phase Locked Loops (PLLs) are available as embedded hard-macros in the latest Field Programmable Gate Arrays (FPGAs). Their main features are clock phase de-skewing, frequency multiplication and division. Moreover, the availability of PLLs allows the user to perform jitter filtering too. The clock signal at the output of a DLL or a PLL has a phase noise, which has to be taken into account in timing sensitive applications, such as analog-to-digital conversion, time measurements or high-speed serial links.

Design of a 12-Bit 2.5 MS/s Integrated Multi-Channel Single-Ramp Analog-to-Digital Converter for Imaging Detector Systems

This paper presents a novel design of a 12-bit multi-channel single-ramp analog-to-digital converter (ADC) for imaging detector systems. To overcome the problem of long conversion time in the classic Wilkinson ADC, a new architecture using a counter and delay line interpolations is proposed. Two 5-bit Gray counters are designed for the coarse conversion. The time interpolation using an array of five delay-locked loops (DLLs) and the multiphase sampling technique are proposed for the fine conversion. The 140-phase delay clocks are generated by the array and pseudo 7-bit fine resolution is achieved. A one-channel prototype chip is implemented in AMS 0.35 μm CMOS technology. The total conversion time is about 400 ns, which corresponds to a sampling rate of 2.5 MS/s. The proposed ADC can be utilized in many fields, such as high-energy physics, biomedical imaging, and space applications.

Autonomous, Multilevel Ring Tuning Scheme for Post-Silicon Active Clock Deskewing Over Intra-Die Variations

Synchronous clock distribution continues to be the dominant timing methodology for VLSI circuit designs. As processes shrink, clock speeds increase, and die sizes grow, an increasingly larger percentage of the clock period is being lost to skew and jitter budgets. Process, voltage, and temperature variations, especially those that are intra-die, increasingly upset the distribution of a synchronized clock signal, even in properly balanced clock tree networks. As a result, active clock deskewing systems are becoming necessary to tune out unwanted clock skew after chip fabrication. This paper first defines the operation of a specially designed phase detector, referred to as an up/down detector (UDD). Next, four of these UDDs are used as links to construct a stable, autonomously locking quadrantal ring tuning (QRT) configuration that effectively joins together four distributed delay-locked loops (DLLs) without the need for any system-level controller. This cyclic, self-controlled, quad-DLL ring tuning technique is then implemented hierarchically to dynamically adjust clock signal delays across an entire chip during normal circuit operation. A simplistic two-level QRT system is presented for a generic H-tree clock distribution network, demonstrating stable locking behavior and more than 50% average reduction in overall clock skew.

Development of a Low-Noise Front-End Readout Chip Integrated With a High-Resolution TDC for APD-Based Small-Animal PET

This paper presents the design of a low-noise multi-channel front-end readout chip integrated with a high-resolution TDC. It is foreseen to be used as front-end readout electronics of Avalanche Photo Diodes (APD) dedicated to a small animal Positron Emission Tomography (PET) system. The architecture of the chip is reported. Two prototype chips, a ten-channel front-end chip and a three-channel high-resolution TDC, have been designed in AMS 0.35 μm CMOS technology. A low-noise charge-sensitive amplifier (CSA) and a shaper are integrated in each channel of the front-end chip. The proposed CSA performs a compensation of the 40 nA dark current coming from the detector. An equivalent input noise charge of 275 e- + 10 e-/pF (rms) has been obtained from test. The TDC chip is based on coarse-fine two-level conversion scheme. In the coarse conversion, a 10-bit counter is employed to achieve a wide range. Meanwhile, the time interpolation using an array of delay-locked loops is proposed for fine conversion. The measured time range is 10 μs. The bin size has been achieved from 71 ps to 142 ps with a reference clock from 100 MHz to 50 MHz.

An analysis of delay-locked loop tracking binary Markovian sequence in the presence of multiple access interference and channel noise

This paper presents an analysis of delay-locked loops in direct spreading code division multiple access systems with Markovian spreading sequences. The established analysis with piecewise constant approximation is similar to the mean field analysis which estimates macroscopic characteristics of a spatially-distributed probabilistic system from the local interaction between the elements of the system with low computational complexity. The low complexity makes it possible to analyze the behavior of not only second-order archetype delay-locked loops but also higher-order non-coherent delay-locked loops in the presence of both multiple access interference and channel noise. It is found from the presented analysis that replacing i.i.d. spreading sequences with Markovian spreading sequences with non-vanishing negative autocorrelation reduces the phase tracking error of a non-coherent 1Δ delay-locked loop. The time spent for estimating the error by the presented method is about 1/1000 compared with that by the path integral method.

An RHBD Technique to Mitigate Missing Pulses in Delay Locked Loops

A radiation-hardened-by-design (RHBD) voltage- controlled delay line (VCDL) for single-event mitigation in delay-locked loops (DLLs) is proposed. A modified fully differential delay cell topology is used to harden the VCDL, resulting in a dramatic reduction of the missing pulses generated by the DLL after an ion strike. By increasing the width-to-length ratios of the feedback transistors of the VCDL delay cells, this topology provides substantially reduced single-event errors while maintaining high operating frequency, wide tuning range and small area penalty.

A 14.6 ps Resolution, 50 ns Input-Range Cyclic Time-to-Digital Converter Using Fractional Difference Conversion Method

This paper presents a time-to-digital converter (TDC) using a fractional difference conversion scheme. Two delay-locked loops (DLLs) provide negative feedbacks to stabilize the delays against process and ambient variations. In addition, by adopting the principles of cyclic Vernier delay line, the resolution is improved while dynamic range is significantly increased. The proposed TDC architecture is competitive in terms of resolution and power compared to the other DLL/PLL stabilized TDCs. The TDC designed and fabricated in 0.18 μm CMOS process achieves a 14.6 ps resolution as well as a 50 ns dynamic range, while consuming 6.4 mW power.

Mathematical model of physical RNGs based on coherent sampling

ABSTRACT Random number generators represent one of basic cryptographic primitives used in creating cryptographic protocols. Their security evaluation represents very important part in the design, implementation and employment phase of the generator. One of important security requirements is the existence of a mathematical model describing the physical noise source and the statistical properties of the digitized noise derived from it. The aim of this paper is to propose the model of a class of generators using two jittery clocks with rationally related frequencies. The clock signals with related frequencies can be obtained using phase-locked loops, delay-locked loops or ring oscillators with adjusted oscillation periods. The proposed mathematical model is used to provide entropy per bit estimators and expected bias on the generated sequence. The model is validated by hardware experiments.

Tunable SEU-Tolerant Latch

This paper presents a single event upset (SEU) hardened latch that can mitigate SEU pulses having a width less than T, where T is the longest anticipated duration of SEUs. The propose latch includes a controllable inertial delay inverter. In order to mitigate SEUs with pulse widths less than T, a global controller uses delay locked loops to control the rise and fall times of the controllable inertial delay inverter in each latch to be equal to T. This allows T to be adjustable for different applications and environmental conditions. This technique introduces little area penalty and does not adversely affect propagation delay.

Low-Complexity All-Digital Sample Clock Dither for OFDM Timing Recovery

Based on phase adjustment, this work investigates a low-complexity all-digital sample clock dither (ADSCD) to perform coherent sampling for orthogonal frequency-division multiplexing (OFDM) timing recovery. To reduce complexity, only tri-state buffers are acquired to build a multiphase all-digital clock management (ADCM), which can generate more than 32 phases over gigahertz without phase-locked or delay-locked loops. Following divide-and-conquer search and triangulated approximation, the phase adjustment is simple but efficient, such that four preambles are adequate to make analog-to-digital (A/D) sampling coherent. Performance evaluation indicates that the proposed ADSCD can tolerate ±400-ppm clock offsets with 0.8 ~ 1.3-dB signal-to-noise ratio (SNR) losses at 8% PER in frequency-selective fading. Hence, this scheme involves a little overhead to ensure fast recovery and wide offset tolerance for OFDM packet transmissions.