Using D flip-flop with reset terminal to design PFD in QCA nanotechnology

Abstract

ABSTRACT Quantum-dot cellular automata (QCA), which has very high speed and very low area and power consumption, is one of the proposed nanotechnologies to design digital electronic circuits. Phase-locked loops (PLLs) and delay-locked loops (DLLs) are two important blocks in transceiver circuit design. The phase-frequency detector (PFD), which measures the phase and frequency differences of two signals, is one of the main blocks in PLLs and DLLs architectures. In this paper, two novel phase-frequency detector designs have been proposed in QCA technology using rising and falling edge D flip-flops with reset ability. The proposed PFDs can provide the basis for designing larger circuits such as phase-locked loops and delay-locked loops that are widely used in communication systems. The two proposed structures for the phase-sensitive detector in quantum cellular automata technology, which detect the phase differences of rising and falling edges of their inputs, are composed of 174 and 170 cells, occupying only 0.27 and 0.26 μm2, respectively. Smaller area, better jitter performance, smaller glitch and reset path time, higher operating frequency and lower power consumption are the main advantages of proposed designs in comparison with CMOS PFDs. All the simulations are done by QCADesigner software and QCAPro Software.