MOSFET Degradation Research Articles

AC-Stress Degradation and Its Anneal in SiC MOSFETs

Several important aspects related to the phenomena of ac gate-bias stress-induced threshold-voltage degradation in SiC MOSFETs are presented. These include a detailed investigation of the particular sensitivity of trench-geometry devices when exposed to a negative gate-bias overstress, the specific conditions that drive this degradation, and its recovery by the application of a dc negative bias temperature stress.

Detailed total ionizing dose effects on LDMOS transistors

The degradation of lateral double-diffused MOSFETs (LDMOS) due to total ionizing dose (TID) effects is examined in this paper using physics-based 2D TCAD simulations. The devices under test (DUTs) are built with a single reduced surface field (single-RESURF) structure and local oxidation of silicon (LOCOS) field oxide. The device structure was chosen for its topological simplicity in comparison to other modern LDMOS transistors to explore the impact of gamma radiation on small-AC and RF behavior. The results demonstrate fundamental differences between n-type (nLDMOS) and the p-type (pLDMOS) parameter shifts. Due to the distinct damage location in the pLDMOS, which is mainly the drift region, TID augments the values of the various parasitic capacitances. However, in the nLDMOS, TID reduced those values, especially the gate capacitance overshoot, as the degradation happens in the channel region and the bird's beak mostly. Consequently, the RF response and stability of the devices will differ. In addition, we present new research opportunities for TID effects on LDMOS transistors in particular, but also for radiation studies in general.

Evidence of Hot-Hole Induced Degradation in Lateral NDRIFT MOSFET: Characterization and TCAD Analysis

The role of secondary hot holes in the degradation of n-channel lateral drift MOSFETs, possibly leading to gate oxide breakdown, is discussed. Trapping of positive charges in the gate and field oxides and the formation of interface states under hot-carrier stress (HCS) have been successfully monitored by means of direct current current-voltage (DCIV) measurements and through gate-drain capacitance measurements. Experimental data have been complemented with Technology Computer Aided Design (TCAD) analysis. A degradation model including both hot-electrons and secondary hot-holes induced degradation capable of interpreting and reproducing measured data is proposed. Simulations allow to gain insights in the kinetics laws governing charge trapping and interface states generation along the silicon/oxide interface. The drift kinetics of the ON-state resistance have been also characterized and reproduced by simulations.

Application of Total Ionizing Dose Radiation Test Standards to SiC MOSFETs

The total ionizing dose (TID) test standards have been developed based on silicon devices to evaluate the TID response of MOS devices for space use. To estimate the applicability of the existing TID test standards to the wide-gap semiconductor silicon carbide (SiC) devices, 1200 V SiC n-channel MOSFETs from three manufacturers were irradiated with Cobalt-60 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\gamma $ </tex-math></inline-formula> -rays at the high radiation dose rate of 50 rad(Si)/s and the low radiation dose rate of 0.01 rad(Si)/s, respectively. The threshold voltage of devices under test (DUT) shifted toward negative due to the radiation-induced positive oxide trapped charges. Room temperature (RT) anneal of maximum time of 2100 h and high temperature (HT) accelerated anneal of maximum temperature of 105 °C were performed, causing the threshold voltage shift to recover. The synergetic effects of temperature-gate-bias stress and TID on SiC MOSFETs were experimentally studied. In conclusion, the degradation of SiC MOSFETs irradiated at high dose rate is dominated by the positive trapped oxide charges, and the existing TID test standards are applicable to evaluate the SiC MOSFETs radiation hardness level, but the threshold voltages shift due to HT-gate-bias (HTGB) should be evaluated.

Impact of Hot-Carrier Degradation Due to Moisture Diffusion Based on 0.153um CMOS

The study aims to investigate enhanced hot-carrier-induced degradation of MOSFETs due to moisture diffusion from inter-metal oxides. By studying different split of back-end in details, it is confirmed the impact of hot-carrier-induced degradation due to moisture diffusion under different conditions. Analyzing how much current drops after 10K times of programming and erasing verifies the cause of device degradation. Experimental results indicate that HDP thickness reduction, alloy after HDP, deposition of SRO layer before HDP and material of TEOS can efficiently enhance hot-carrier-induced degradation. According to the experimental results, the influence of moisture diffusion has been clarified, providing directions for enhancing the hot-carrier-induced degradation of MOSFETs, and providing relevant experience for subsequent product development.

Degradation in super-junction MOSFET under successive exposure of heavy ion strike and gamma ray irradiation

The degradation of 200 V super-junction MOSFET under successive exposure of heavy ion strike and gamma ray irradiation is investigated for the first time in this paper. Compared with the device purely irradiated with gamma ray, the MOSFET subjected to superimposed irradiation stress, e.g. irradiated with heavy ion strike first and then irradiated with gamma ray, exhibits more serious deterioration in static characteristics, such as threshold voltage and transconductance. Moreover, the devices under superimposed irradiation stress exhibits very different dynamic characteristics, such as more obviously increased gate charges and improved reverse recovery. In addition, the degradation mentioned above caused by the extra oxide traps and interface strain bonds generated by heavy ion strike can be attenuated with applying negative gate voltage bias during the whole experiments, which provides a solution to avoid this potential threat in aerospace application.

Degradation and breakdown behaviors of SGTs under repetitive unclamped inductive switching avalanche stress

The repetitive unclamped inductive switching (UIS) avalanche stress is conducted to investigate the degradation and breakdown behaviors of conventional shield gate trench MOSFET (C-SGT) and P-ring SGT MOSFETs (P-SGT). It is found that the static and dynamic parameters of both devices show different degrees of degradation. Combining experimental and simulation results, the hot holes trapped into the Si/SiO2 interface and the increase of crystal lattice temperature should be responsible for the degradation and breakdown behaviors. Moreover, under repetitive UIS avalanche stress, the reliability of P-SGT overcomes that of C-SGT, benefitting from the decreasing of the impact ionization rate at bottom of field oxide caused by the existence of P-ring.

Modeling of Bipolar Degradations in 4H-SiC Power MOSFET Devices by a 3C-SiC Inclusive Layer Consideration in the Drift Region

The reliability of 4H-SiC power devices account not only to power packages but as well to SiC materials which contain defects that impact the performance of power converters. A detrimental material defect that is still hindering the development of high power MOSFET devices is the so-called bipolar degradation. It is mainly due to Shockley stacking sequence faults (SFs) within the hexagonal SiC structure lattice creating 3C-SiC- regions embedded within the main 4H-SiC structure. In this paper, we have modelled the bipolar degradation of a power MOSFET device rated at 1.7kV by considering the drift layer formed by a 4H-3C-4H heterojunction. In term of electrical parameters, the bipolar degradation which manifests itself as the increase of the forward voltage of the device, TCAD simulation results showed an increase of 0.7 V and 1 V of the forward voltage at a current level of -3A and 4A for the body diode and the MOSFET operating in the first quadrant respectively. These were of the same order of magnitude as experimental results obtained on degraded power MOSFET devices. Additionally, we have presented a novel method to ascertain the presence of SFs within the power device by measuring the electroluminescence of the body diode.

Investigation on the passivation, band alignment, gate charge, and mobility degradation of the Ge MOSFET with a GeO x /Al2O3 gate stack by ozone oxidation

Ge has been an alternative channel material for the performance enhancement of complementary metal–oxide–semiconductor (CMOS) technology applications because of its high carrier mobility and superior compatibility with Si CMOS technology. The gate structure plays a key role on the electrical property. In this paper, the property of Ge MOSFET with Al2O3/GeO x /Ge stack by ozone oxidation is reviewed. The GeO x passivation mechanism by ozone oxidation and band alignment of Al2O3/GeO x /Ge stack is described. In addition, the charge distribution in the gate stack and remote Coulomb scattering on carrier mobility is also presented. The surface passivation is mainly attributed to the high oxidation state of Ge. The energy band alignment is well explained by the gap state theory. The charge distribution is quantitatively characterized and it is found that the gate charges make a great degradation on carrier mobility. These investigations help to provide an impressive understanding and a possible instructive method to improve the performance of Ge devices.

Hot Carrier Degradation in MOSFETs at Cryogenic Temperatures Down to 4.2 K

Wide attention has been focused on cryogenic CMOS (cryo-CMOS) operation because of its promising improvement of devices’ and circuits’ performance and wide application prospects. However, hot carrier degradation (HCD) limits the long-term reliability of cryo-CMOS. This article investigates HCD in 0.18 μm bulk CMOS at cryogenic temperature down to 4.2 K. Particularly, the relationship between HCD and the current overshoot phenomenon and the influence of substrate bias on HCD are discussed. Besides, we predict the lifetime of the device at 77 K and 4.2 K. It is concluded that cryogenic NMOS cannot reach the ten years’ commercial standard lifetime at standard VDD. And it is predicted that the reliability requirements can be reached when VDD≤1.768 V and 1.734 V at 77 K and 4.2 K, respectively. Differently, the lifetime of PMOS is long enough even at low temperatures.

Investigating the Impact of Self-Heating Effects on some Thermal and Electrical Characteristics of Dielectric Pocket Gate-all-around (DPGAA) MOSFETs

The dielectric pocket gate-all-around (DPGAA) MOSFET is being considered the best suited candidate for ULSI electronic chips because of excellent electrostatic control over the channel. However, the phenomena of self-heating and hot carrier injection (HCI) severely affect the performance of the device, and make the behaviour of the DPGAA FET very unpredictable. In the present article, a comprehensive investigation under the influence of self-heating effects has been done for the variation in the lattice and carrier temperature against spacer length, ambient temperature, device length, and thermal contact resistance including ON and Off currents with gate bias voltage (VGS). In order to analyse the SHEs, the hydrodynamic (HD) and thermodynamic (TD) transport models have been used for three-dimensional (3D) electrothermal (ET) simulation. The Lucky (hot carrier injection) model has been used to study the HCI degradation in DPGAA MOSFET using Sentaurus 3D TCAD simulator.

Investigation of breakdown voltage degradation in low-voltage narrow gate trench MOSFET by edge termination optimization

In this paper, we investigate breakdown voltage degradation in a 25 V low-voltage narrow gate (NG) shield-gate trench MOSFET (NG-SGTMOS). Experiments and simulations based on Technology Computer-Aided Design (TCAD) indicate that electric field crowding and parasitic bipolar junction transistor (BJT) punch-through are responsible for the degradation of the device breakdown characteristic. To address these issues, two critical parameters, t 1 and t 2, are optimized in the layout of the transition and termination regions of the experimental NG-SGTMOS. It is demonstrated that electric field crowding induced by excessive and non-full depletion in edge termination is successfully eliminated at t 1 = 0.6 μm. Moreover, when improving t 2 beyond 0.2 μm, the soft breakdown characteristic owing to parasitic npn-BJT punch-through can be suppressed. As a result, the breakdown voltage stability of the proposed low-voltage NG-SGTMOS is improved.

Modeling of interface trap charges induced degradation in underlap DG and GAA MOSFETs

With the shrinking device geometries, the extremely high electric field in the drain-channel region makes nano-devices more susceptible to Hot Carrier induced Degradation (HCD) effects. This paper develops an HCD degradation model of gate underlap Double Gate (DG) and Gate All Around (GAA) MOSFET due to hot carrier induced interface trap charges (ITCs). The parabolic approximation and conformal mapping techniques are used to solve the 2D Poissons equation to obtain the channel potential function of the device. The modeling results show that the ITCs effect becomes more dominant for scaled-down DG and GAA MOSFETs and can be reduced by the underlap design. The proposed model accurately depicts the interface charges induced degradation on surface potential, threshold voltage, and Drain Induced Barrier Lowering (DIBL). The effect of ITCs on the threshold voltage and DIBL with the variation of underlap length, gate length, oxide thickness and damaged region length are investigated and validated by comparing them with their corresponding TCAD simulation data obtained by using the TCAD Sentaurus. From the results, it is observed that the effect of negative ITCs (NITCs) have more dominant effect in comparison to positive ITCs (PITCs), and GAA with underlap are more immune to the ITCs effect in comparison to DG MOSFETs. The proposed model is useful in reducing short channel effects in DG/GAA devices to increase immunity against SCEs and useful in practical devices.

Mobility degradation in 4H-SiC MOSFETs and interfacial formation of carbon clusters

We describe a detailed atomic model of the SiC/SiO2 interface states due to carbon clusters which lower the field effect mobility of SiC below its Hall effect value, due to the oxidation process. The carbon clusters are on the SiO2 side. We show for the first time that carbon clusters containing a mixture of sp2 and sp3 sites explain the results, with these sp2 sites forming small sub-clusters to maintain a large local band gap.

Analysis and modeling for MOSFET degradation under RF stress

Analysis and modeling for MOSFET degradation under RF stress

Impact of Temperature Variation on Analog, Hot-Carrier Injection and Linearity Parameters of Nanotube Junctionless Double-Gate-All-Around (NJL-DGAA) MOSFETs

Silicon-based Nanotube Junction-less Double-Gate-All-Around (NJL-DGAA) MOSFETs has become a promising solution to high-speed ULSI chip design. However, the change in surrounding temperature affects its performances, such as hot carrier injection (HCI) degradation, Linearity distortion, and analog performance, which are to be critically analyzed. In the present paper, the analog performance, HCI degradation, and Linearity distortion of NJL-DGAA MOSFETs are investigated on temperatures ranging from 200K to 500K using a Sentaurus 3D device simulator. The parameters such as ON-current, OFF-current, DIBL, subthreshold swing (SS), transconductance, gate leakage current, high-order gm, VIP2, VIP3, IIP3, IMD3, and 1-dB compression point have been evaluated for the mentioned temperature range. The ON-current and DIBL are found to be increased by 17.2 % and 27.5 %, respectively, when the temperature increases from 200K to 500K. However, assessment of performance reveals that the NJL-DGAA devices offer superior analog performance with high-frequency applications even at higher temperature ranges.

The Relationship Between Resistive Protective Oxide (RPO) and Hot Carrier Stress (HCS) Degradation in n-Channel LD SOI MOSFET

This article investigates the influence of resistive protective oxide (RPO) layer density and hot carrier stress (HCS) degradation in n-channel lateral diffused silicon-on-insulator metal–oxide–semiconductor field-effect transistors. At the beginning of HCS at a higher gate voltage ( ${V}_{G}$ ), the threshold voltage shifts and subthreshold swing increase, but the ON-state current will still increase abnormally. The drain current and drain voltage ( ${I}_{D}$ – ${V}_{D}$ ) transfer curves indicate that channel resistance or drift region resistance dominates degradation between low- ${V}_{G}$ and high- ${V}_{G}$ respectively. It also found different degradation behavior by extracting the resistances at low- ${V}_{G}$ and high- ${V}_{G}$ to stress time. In addition, technology computer-aided design (TCAD) software results show maximum impact ionization of high- ${V}_{G}$ , in which the direction of the electric field is toward RPO, resulting in the injection of holes into RPO during HCS. Finally, the simulated drain current and gate overdrive voltage curves for numerous interface states and numerous oxide traps show that the abnormal ${I}_{ \mathrm{\scriptscriptstyle ON}}$ enhancement is due to the hole trapping in the RPO and the degradation is closely related to the different density of RPO. In this article, we determine the mechanism of HCS degradation and propose methods to optimize high-voltage (HV) device performance and reliability.

Carbon cluster formation and mobility degradation in 4H-SiC MOSFETs

The performance of SiC MOSFETs is limited by many defects at the SiC/SiO2 interface. However, there are no fully consistent atomic models of these defects or how their large densities arise. We show how the high heat of formation of SiO2 causes a selective oxidation of Si in SiC, leaving carbon clusters in SiO2. We consider chemical potentials across the interface from both the thermochemical and oxidation kinetics viewpoint. SiO2 native defects give states too far in energy from the SiC band edges, while defects in bulk SiC have too high a formation energy. Only carbon clusters have a low enough formation energy to give sufficient defect densities to account for the mobility loss, and experimental evidence for them is discussed.

Determination of Power MOSFET’s Gate Oxide Degradation Under Different Electrical Stress Levels Based on Stress-Induced Oxide Capacitance Changes

In this article, we aim to investigate the gate oxide degradation of power MOSFETs through oxide capacitance. We focus on modeling the oxide capacitance variation as a function of several stress levels and time intervals. The experimental procedure is carried out by means of commercial n-channel vertical double-diffused metal-oxide semiconductor field-effect transistors (VDMOSFETs) that have maximum voltage and current ratings as 200 V and 5.2A, respectively. We calculate the oxide capacitance using measurable reverse capacitance that is equal to gate–drain capacitance. The turn-around point is determined at each stress level. We observe that the oxide capacitance shows a nonlinear variation due to the stress time and level. The variation is divided into two regions for the model. The modeling procedure starts with the mathematical fitting. The equations are obtained by using curve fitting methods. The circuit model is designed via SPICE Simulation by using these equations. We also consider the turn-around points for the circuit design. The simulation and experimental results have good compatibility. We achieve 92.3% and 90.8% similarity on average for first and second region of the variation, respectively.

Modelling and Failure Analysis of SiC MOSFET under the Effects of Parasitic Parameters

Recent years, SiC MOSFET has been gradually utilized in high power devices. However, it has become one of the highest failure rate devices in circuit systems. Its failure relates to the degradation which caused by the hot carrier injection(HCI) effect. Because the parasitic parameters make the oscillations in switching processes more intense, the switching time and voltage overshoot increases, and thus HCI effect exacerbates. So, it is necessary to analyse the influence of parasitic parameters on the failure of SiC MOSFET. In this paper, an improved SiC MOSFET model with all key parasitic parameters is built to set up an accurate test circuit. The parasitic parameters were divided into four parts: body diode, parasitic resistance, parasitic capacitance and parasitic inductance. According to the simulation, it concluded that only the parasitic inductance has a great impact on the HCI effect and the impacts are different according to the different locations of parasitic inductance. The influence of the parasitic inductance on the load circuit and near the source is much greater than other parts. Their increase greatly increases switching time and voltage overshoot, and thus exacerbates HCI effect and accelerates the degradation of SiC MOSFET.