Modeling of Bipolar Degradations in 4H-SiC Power MOSFET Devices by a 3C-SiC Inclusive Layer Consideration in the Drift Region

Abstract

The reliability of 4H-SiC power devices account not only to power packages but as well to SiC materials which contain defects that impact the performance of power converters. A detrimental material defect that is still hindering the development of high power MOSFET devices is the so-called bipolar degradation. It is mainly due to Shockley stacking sequence faults (SFs) within the hexagonal SiC structure lattice creating 3C-SiC- regions embedded within the main 4H-SiC structure. In this paper, we have modelled the bipolar degradation of a power MOSFET device rated at 1.7kV by considering the drift layer formed by a 4H-3C-4H heterojunction. In term of electrical parameters, the bipolar degradation which manifests itself as the increase of the forward voltage of the device, TCAD simulation results showed an increase of 0.7 V and 1 V of the forward voltage at a current level of -3A and 4A for the body diode and the MOSFET operating in the first quadrant respectively. These were of the same order of magnitude as experimental results obtained on degraded power MOSFET devices. Additionally, we have presented a novel method to ascertain the presence of SFs within the power device by measuring the electroluminescence of the body diode.