Abstract
The total ionizing dose (TID) test standards have been developed based on silicon devices to evaluate the TID response of MOS devices for space use. To estimate the applicability of the existing TID test standards to the wide-gap semiconductor silicon carbide (SiC) devices, 1200 V SiC n-channel MOSFETs from three manufacturers were irradiated with Cobalt-60 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\gamma $ </tex-math></inline-formula> -rays at the high radiation dose rate of 50 rad(Si)/s and the low radiation dose rate of 0.01 rad(Si)/s, respectively. The threshold voltage of devices under test (DUT) shifted toward negative due to the radiation-induced positive oxide trapped charges. Room temperature (RT) anneal of maximum time of 2100 h and high temperature (HT) accelerated anneal of maximum temperature of 105 °C were performed, causing the threshold voltage shift to recover. The synergetic effects of temperature-gate-bias stress and TID on SiC MOSFETs were experimentally studied. In conclusion, the degradation of SiC MOSFETs irradiated at high dose rate is dominated by the positive trapped oxide charges, and the existing TID test standards are applicable to evaluate the SiC MOSFETs radiation hardness level, but the threshold voltages shift due to HT-gate-bias (HTGB) should be evaluated.
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