Degradation Of Device Parameters Research Articles

Self-heating of stressed VDMOS devices under specific operating conditions

This paper gives insight into the self-heating effects and combination of self-heating and NBTI effects in p-channel power VDMOS transistors. NBTI effects lead to the degradation of device parameters, where threshold voltage (VT) is the most important one, since it directly affects the device's safe operating area and lifetime. Effects were analysed using images from an infrared thermographic camera taken under different drain currents and controlling signal waveforms. Results point out that the self-heating of the previously stressed devices is more emphasized and that it proposes additional limitations in the terms of the device's reliability.

Accurate analytical models of hot carrier degradation in nMOSFET and nFinFET considering saturation effect

In this paper, models of hot carrier degradation (HCD) in nMOSFET and nFinFET, combined with the physical mechanism and reaction-diffusion framework and considering saturation effect, are proposed. The HCD data of different technology nodes of nMOSFET and nFinFET are used to verify the accuracy of the models. The results show that the prediction errors of device parameter degradation under different stress voltages are less than 10% for several types of short channel devices, which is better than the existing reported research results. Furthermore, the models have simple analytical expressions that allow them to not only be applied to device HCD prediction, but also be extended to circuit level HCD prediction tool more easily.

Flexible kesterite thin-film solar cells under stress

Understanding the stress-induced phenomena is essential for improving the long-term application of flexible solar cells to non-flat surfaces. Here, we investigated the electronic band structure and carrier transport mechanism of Cu2ZnSn(S,Se)4 (CZTSSe) photovoltaic devices under mechanical stress. Highly efficient flexible CZTSSe devices were fabricated controlling the Na incorporation. The electronic structure of CZTSSe was deformed with stress as the band gap, valence band edge, and work function changed. Electrical properties of the bent CZTSSe surface were probed by Kelvin probe force microscopy and the CZTSSe with Na showed less degraded carrier transport compared to the CZTSSe without Na. The local open-circuit voltage (VOC) on the bent CZTSSe surface decreased due to limited carrier excitation. The reduction of local VOC occurred larger with convex bending than in concave bending, which is consistent with the degradation of device parameters. This study paves the way for understanding the stress-induced optoelectronic changes in flexible photovoltaic devices.

Analysis of DC Characteristics in PDSOI pMOSFETs Under the Combined Effect of NBTI and TID

The influence of DC characteristics in PDSOI pMOSFETs under different NBTI and TID conditions was investigated. The threshold voltage, trans-conductance, and subthreshold swing of the devices were compared before and after irradiation under NBTI conditions, and the lifetime of the devices was predicted. The contributions of interface-trap charges and oxide-trap charges to the threshold voltage degradation were analyzed under the combined effect of TID and NBTI. Based on the R-D model, the degradation of device parameters under the combined effect of TID and NBTI was explained in this paper.

A Charge-Based Analytical Model for Gate All Around Junction-Less Field Effect Transistor Including Interface Traps

This article proposes an analytic charge-based model that incorporates interface trapping. The model’s applicability to all operating zones includes various interface trap charges with varying doping concentrations. Using the analytical model, the impact of interface traps on different electrical parameters, such as channel potential, surface potential, electric field, and drain current, is examined. The transconductance and cut-off frequency models are also developed from the drain current model. To validate our model, the analytical model results were compared with the TCAD device simulation results and available experimental data from literature. The Fermi level location of interface traps greatly influences surface potential in the bandgap, leading to subthreshold deterioration and flat band shifting in Junction Less Field Effect Transistor (GAAJLFET) with SiO2 as a gate insulator, which leads to performance degradation of different device parameters. To decrease the impact of the interface trap on the device’s characteristics without impairing the performance, a suitable device with SiO2 and high-k gate-stack as an insulator is designed and compared with GAAJLFET with SiO2 as a gate insulator. A GAAJLFET with SiO2 as an insulating material has very different device parameters than a GAAJLFET with SiO2 and high-k gate-stack as a gate insulating material.

NBTI-Aware Power Gating Design with Dynamically Varying Stress Probability Control on Sleep Transistor

With the aggressive scaling of the transistor, Negative Bias Temperature Instability (NBTI) has become the most dominant aging effect which causes the device parameter to degrade over its lifetime. This device parameter degradation of logic gates in nanometer technology is a major concern for the reliability of the digital circuit. It becomes even more critical when it comes to power gating structure, as small NBTI effect on PMOS sleep transistor used in header-based power gating structure would seriously affect the reliability, performance of the whole logic circuit. The conventional method of mitigating the NBTI effect is to oversize the sleep transistor, but it also gives rise to leakage overhead. In this work, a novel NBTI aware power gating architecture is presented to improve the lifetime of the circuit. Here, sleep transistors (STs) are switched ON/OFF periodically and a greater number of STs are turned ON, when NBTI related degradation reaches to its threshold value so that STs get more time to anneal NBTI degradation and improve its lifetime. Simulation result on ISCAS’85 benchmark circuits shows for 40% sleep signal, an average of 51.2% and 14% lifetime improvement with respect to the conventional over-sizing (OS) technique and normal stress probability control method, respectively with some power and area overhead.

High energy swift heavy ion irradiation and annealing effects on DC electrical characteristics of 200 GHz SiGe HBTs

Abstract The total ionizing dose (TID) and non ionizing energy loss (NIEL) effects of 100 MeV phosphorous (P7+) and 80 MeV nitrogen (N6+) ions on 200 GHz silicon-germanium heterojunction bipolar transistors (SiGe HBTs) were examined in the total dose range from 1 to 100 Mrad(Si). The in-situ I–V characteristics like Gummel characteristics, excess base current (ΔIB), net oxide trapped charge (NOX), current gain (hFE), avalanche multiplication (M − 1), neutral base recombination (NBR) and output characteristics (IC-VCE) were analysed before and after irradiation. The significant degradation in device parameters was observed after 100 MeV P7+ and 80 MeV N6+ ion irradiation. The 100 MeV P7+ ions create more damage in the SiGe HBT structure and in turn degrade the electrical characteristics of SiGe HBTs more when compared to 80 MeV N6+. The SiGe HBTs irradiated up to 100 Mrad of total dose were annealed from 50 °C to 400 °C in different steps for 30 min duration in order to study the recovery of electrical characteristics. The recovery factors (RFs) are employed to analyse the contribution of room temperature and isochronal annealing in total recovery.

A Comparison of Electron, Proton and Gamma Irradiation Effects on the I-V Characteristics of 200 GHz SiGe HBTs

Total ionizing dose effects induced by 1 MeV electron and 5 MeV proton on the dc electrical characteristics of 200 GHz silicon germanium heterojunction bipolar transistors (SiGe HBTs) were investigated. These results were compared with 60Co gamma irradiation results to understand the linear energy transfer effects on the electrical characteristics of SiGe HBTs. The different electrical parameters like forward and inverse mode Gummel characteristics, excess base current ( ${\boldsymbol \Delta } I_{\mathbf {B}}$ ), current gain ( $\boldsymbol {h}_{\mathbf {FE}}$ ), and output characteristics ( $\boldsymbol {I}_{\mathbf {C}}$ - $\boldsymbol {V}_{\mathbf {CE}}$ ) were systematically studied before and after irradiation. The electrical characteristics of irradiated SiGe HBTs degrade with an increase in total dose. The more degradation in device parameters was observed in case of 5 MeV proton irradiated HBTs when compared to other radiations. The irradiated devices were also subjected to isochronal annealing to analyze the recovery of electrical parameters.

An Effective Method to Compensate Total Ionizing Dose-Induced Degradation on Double-SOI Structure

The existence of buried oxide (BOX) layer and the strong coupling effect between the front and back channels can worsen the radiation-induced degradation on fully depleted silicon-on-insulator (FDSOI) device. To mitigate the radiation impact, a new structure named double SOI is introduced in this paper. This new structure exhibits potential benefits of reducing the radiation-induced degradation effectively and independently, thanks to the additional electrode, which can be used to control the internal electrical field of the BOX layer. With this structure, FDSOI device parameter degradation due to total dose is studied, and some abnormal phenomena, such as the transconductance hump and the mobility enhancement, are observed and discussed. Sentaurus TCAD simulations are used for further analysis. Moreover, the impact of negative back-gate bias to transistor parameter degradation is investigated, and an improved back-gate compensation strategy is proposed. Technology improvement such as thinning the BOX on total ionizing dose (TID) amelioration is also discussed with TCAD simulation.

Extreme radiation hard thin film CZTSSe solar cell

In this work, we have demonstrated the extreme radiation hardness of thin film CZTSSe solar cells. Thin film solar cells with CZTSSe, CZTS and CIGS absorber layers were irradiated with 3 MeV protons. No degradation in device parameters was observed until a displacement damage dose of 2 × 1010 MeV/g for CZTS and CZTSSe. CIGS solar cells degraded by 13% at the same dose. For the highest proton dose both the CZTSSe and CZTS degraded by 16% while CIGS suffered from 34% degradation in efficiency. The degradation in efficiency maybe attributed to the reduction in the minority carrier lifetime due to radiation induced lattice defects. Comparisons with previously available literature show that our CZTS technology has superior radiation hardness by about two orders of magnitude compared to existing state of the art Si and GaAs technology.

Study of Total-Ionizing-Dose Effects on a Single-Event-Hardened Phase-Locked Loop

The sensitivity of total-ionizing-dose (TID) response on a single-event hardened phase-locked loop (PLL) fabricated in a 130-nm silicon-on-insulator process is investigated. Based on the study of device parameter degradation under radiation exposure, the changes of dc and RF performance of the PLL have been presented. TID experiments on the PLL show that the power-down current increases by 1.5 times, and the tuning range drops by 11.5%. At 600 MHz and up to 500 krad(Si), the integrated phase noise increases by 29.2%, and the reference spur increases by 3.4 dB. Finally, the mechanism underlying impact of TID on the phase noise and reference spur has been discussed comprehensively, which combined measured observations with circuit modeling and simulations.

Modeling the PbI2 formation in perovskite solar cells using XRD/XPS patterns

The impact of prolonged irradiation and air humidity on the stability of perovskite solar cells is modeled using X-ray diffraction and X-ray photoelectron spectroscopy patterns reported in the literature. Light or air-moisture causes the formation of a thin PbI2 or oxide defective layers (in nanoscale) at the interface of perovskite/hole-transport-layer or at the junction with metallic back contact. This thin layer blocks the carrier transport/passivation at the interfaces and cause degradation of device parameters. Variation in thickness of defective layers, changes the XRD and XPS peaks. This allows detection and estimation of the type, crystallinity and thickness of the defective layer. A simple model is developed here to extract the thickness of such thin defective layers formed in nanometer scale at the back region of several perovskite devices. Based on this information, corrected energy band diagram of every device before and after degradation/aging is drawn and discussed in order to obtain insight into the carrier transport and charge collection at the barrier region. In addition, graphene contacted perovskite devices are investigated showing that honey-comb network of graphene contact reduces the effect of aging leading to formation of a thinner defective layer at the perovskite surface compared to perovskite devices with conventional inorganic contacts i.e. Au, Al.

Numerical analysis of degradation kinetics in CdTe thin films

A time-dependent approach is introduced to numerically analyze the degradation of CdS/CdTe thin film photovoltaics under different stress conditions using the SCAPS-1D program. Under the stress conditions of light, temperature or bias, the excess charge carriers (holes/electrons) are created/accumulated within the CdTe layer which leads to a defect generation/increment mostly at the interface. The defect increment specially around the midgap level leads to the degradation of device parameters. Since the excess charge carriers and defect increment are coupled we examine several carrier kinetics such as the linear n- or p-model, bilinear np-model and quadratic n2-model. This comprehensive simulation is consistent with the polycrystalline nature of CdTe materials and their ambiguous degradation mechanism. Simulations are performed for short-circuited and open-circuited devices that are assumed to be also under stress conditions of temperature, dark and light. The degradation rate in the device parameters, variations in band diagrams and current–voltage characteristics are analyzed and compared with the relevant experimental reports in literature. As a novelty, our analyses indicate that the degradation rate caused by the linear kinetics of the holes competes with the nonlinear kinetics of the electrons. Thus, holes can lead to a stronger degradation than that of electrons because of their smaller mobility in CdTe materials. Dividing the CdTe layer into several thinner sublayers in the SCAPS platform allows us to analyze the effect of the defect increment position on the device degradation. It is shown that the junction is critically sensitive to defects and charge carrier accumulation. These simulations reveal that the location of carrier/defect accumulation can be just as important as the carrier type and concentration. This simulation approach can be extended to other thin film materials, dye cells and perovskite materials and also to photodetectors and CMOS devices.

Device Area Scale‐Up and Improvement of SWNT/Si Solar Cells Using Silver Nanowires

DOI: 10.1002/aenm.201400186 Si solar cells. This difference becomes more problematic during the scale up to larger size cells, because the total resistive power loss per unit area ( P R ) scales with the cell area. [ 17 ] P R is given by / / R S max 2 s max 2 S max 2 P R I A R J A A R AJ ( ) = = = , where R s is the series resistance in the device, A is the device area, I max and J max are the cell current and current density in the maximum power output respectively. This equation illustrates that the P R is proportional to the product of the series resistance and the area ( R s A ), which directly scales with the cell area. As a result, all the CNT/Si and graphene/Si solar cells with high effi ciency (>10%) reported in the literature are limited with very small junction area (<15 mm 2 ), while the cells with large junction area (≈50 mm 2 ) suffers from very poor effi ciencies (≈1.3%) ( Table 1 ). Besides the effi ciency, a drastic degradation of other device parameters is also observed with a scale-up of the junction-area. For example, Shi et al. reported that the fi ll factor decreased from 72% to 50% when the junction area of graphene/Si solar cells increased from 4.7 mm 2 to 14.5 mm 2 . [ 10 ] A similar reduction of fi ll factor from 45% to 38% was also observed in the scale up of organic solar cells from 2.4 mm 2 to 1.13 cm 2 . [ 18 ]

Impact of Constant Voltage Stress on High-κ Gate Dielectric for RF IC Performance

Challenges in modern CMOS RF IC design include optimizing gain, noise and linearity. These parameters are highly dependent on transconductance (gm) and threshold voltage (Vt). Introduction of high-κ dielectrics with metal gates in advanced CMOS gate stacks requires that the impact of any variation of gm and Vt due to stress on RFIC performance needs to be investigated thoroughly. This paper investigates the effect of positive constant voltage stress (CVS) on device parameter degradation which may have a potential impact on analog and mixed-signal CMOS circuitry. Significant decrease in gm and increase in Vt was observed under CVS due to electron trapping.

Effective Edge Width for 65-nm pMOSFETs and Their Variations Under CHC Stress

The narrow-width W effect of metal-oxide-semiconductor field-effect transistors (MOSFETs) with shallow trench isolation technology has been widely reported. The factor of most concern is the edge width Δw affecting the electrical characteristics of the MOSFETs. In this letter, the negative variation value of Δw, as explained in the content, was derived from 65-nm node p-channel MOSFETs (pMOSFETs). To verify the validity of Δw, the pMOSFETs were stressed by channel-hot-carrier stress conditions. According to the experimental results, the device parameter degradation, i.e., the threshold voltage VTH, was obviously dominated by |Δw|/W, and the degradation of the narrow-width device was also increased for the wide width.

Degradation of polycrystalline silicon TFTs due to alpha particles irradiation stress

The degradation mechanism of poly-Si TFTs due to alpha particles irradiation is investigated. The tested devices exhibit increase in the density of interface states and grain boundaries traps proportional to the radiation fluence, Δ N / N 0 = K ∗ F . The irradiation introduced defects are responsible for the degradation of major device parameters, such as the threshold voltage, the subthreshold swing, the leakage current and the ON mobility and current. Their degradation is found to obey the same law. The analysis of the thermally activated parameters reveals that the irradiation induced defects are lying deep in the semiconductor band gap. Moreover the negative threshold voltage shift is associated to positively charged oxygen vacancies in the gate insulator, called E′ centers.

Angular and Strain Dependence of Heavy-Ions Induced Degradation in SOI FinFETs

We studied the short- and long-term effects of heavy-ion strikes on silicon-on-insulator (SOI) FinFET devices manufactured in a sub 32-nm CMOS process. The degradation of the device DC characteristics after irradiation strongly depends on the incidence angle, strain, and channel type, depending on the balance between damage to the high-k gate oxide and to the buried oxide. The time-dependent dielectric breakdown (TDDB) and the device parameter degradation kinetics are affected by the LET, ion fluence, and incidence angle. A reduction in TDDB is observed in irradiated FinFETs with respect to unirradiated ones.

Study on the degradation of NMOSFETs with ultra-thin gate oxide under channel hot electron stress at high temperature

This paper studies the degradation of device parameters and that of stress induced leakage current (SILC) of thin tunnel gate oxide under channel hot electron (CHE) stress at high temperature by using n-channel metal oxide semiconductor field effect transistors (NMOSFETs) with 1.4-nm gate oxides. The degradation of device parameters under CHE stress exhibits saturating time dependence at high temperature. The emphasis of this paper is on SILC of an ultra-thin-gate-oxide under CHE stress at high temperature. Based on the experimental results, it is found that there is a linear correlation between SILC degradation and Vh degradation in NMOSFETs during CHE stress. A model of the combined effect of oxide trapped negative charges and interface traps is developed to explain the origin of SILC during CHE stress.

Device reliability challenges for modern semiconductor circuit design – a review

Abstract. Product development based on highly integrated semiconductor circuits faces various challenges. To ensure the function of circuits the electrical parameters of every device must be in a specific window. This window is restricted by competing mechanisms like process variations and device degradation (Fig. 1). Degradation mechanisms like Negative Bias Temperature Instability (NBTI) or Hot Carrier Injection (HCI) lead to parameter drifts during operation adding on top of the process variations. The safety margin between real lifetime of MOSFETs and product lifetime requirements decreases at advanced technologies. The assignment of tasks to ensure the product lifetime has to be changed for the future. Up to now technology development has the main responsibility to adjust the technology processes to achieve the required lifetime. In future, reliability can no longer be the task of technology development only. Device degradation becomes a collective challenge for semiconductor technologist, reliability experts and circuit designers. Reliability issues have to be considered in design as well to achieve reliable and competitive products. For this work, designers require support by smart software tools with built-in reliability know how. Design for reliability will be one of the key requirements for modern product designs. An overview will be given of the physical device damage mechanisms, the operation conditions within circuits leading to stress and the impact of the corresponding device parameter degradation on the function of the circuit. Based on this understanding various approaches for Design for Reliability (DfR) will be described. The function of aging simulators will be explained and the flow of circuit-simulation will be described. Furthermore, the difference between full custom and semi custom design and therefore, the different required approaches will be discussed.