Abstract
Challenges in modern CMOS RF IC design include optimizing gain, noise and linearity. These parameters are highly dependent on transconductance (gm) and threshold voltage (Vt). Introduction of high-κ dielectrics with metal gates in advanced CMOS gate stacks requires that the impact of any variation of gm and Vt due to stress on RFIC performance needs to be investigated thoroughly. This paper investigates the effect of positive constant voltage stress (CVS) on device parameter degradation which may have a potential impact on analog and mixed-signal CMOS circuitry. Significant decrease in gm and increase in Vt was observed under CVS due to electron trapping.
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