Abstract
Abstract. Product development based on highly integrated semiconductor circuits faces various challenges. To ensure the function of circuits the electrical parameters of every device must be in a specific window. This window is restricted by competing mechanisms like process variations and device degradation (Fig. 1). Degradation mechanisms like Negative Bias Temperature Instability (NBTI) or Hot Carrier Injection (HCI) lead to parameter drifts during operation adding on top of the process variations. The safety margin between real lifetime of MOSFETs and product lifetime requirements decreases at advanced technologies. The assignment of tasks to ensure the product lifetime has to be changed for the future. Up to now technology development has the main responsibility to adjust the technology processes to achieve the required lifetime. In future, reliability can no longer be the task of technology development only. Device degradation becomes a collective challenge for semiconductor technologist, reliability experts and circuit designers. Reliability issues have to be considered in design as well to achieve reliable and competitive products. For this work, designers require support by smart software tools with built-in reliability know how. Design for reliability will be one of the key requirements for modern product designs. An overview will be given of the physical device damage mechanisms, the operation conditions within circuits leading to stress and the impact of the corresponding device parameter degradation on the function of the circuit. Based on this understanding various approaches for Design for Reliability (DfR) will be described. The function of aging simulators will be explained and the flow of circuit-simulation will be described. Furthermore, the difference between full custom and semi custom design and therefore, the different required approaches will be discussed.
Highlights
Product development based on highly integrated semiconductor circuits faces various challenges
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We focus here on the “Sleep Transistor” approach which is based on leakage power control
Summary
Thewes, R., Walter, G., Brederlow, R., Schlunder, C., von Schwerin, A., Jurk, R., Linnenbank, C. H., Blank, O., Heinrigs, W., Muhlhof, A., Gustin, W., and Schlunder, C.: Analysis of NBTI degradation- and recoverybehavior based on ultra fast VT-measurements, Proceedings IEEE International Reliability Physics Symposium (IRPS), 448– 453, 2006. T., Marshall, A., Rodriguez, J., Natarajan, S., Rost, T., and Krishnan, S.: Impact of negative bias temperature instability on digital circuit reliability, IEEE International Reliability Physics Symposium (IRPS), Proceedings, 7–11 April, 248–254, 2002. Thewes, R., Brederlow, R., Schlunder, C., Wieczorek, P., Hesener, A., Ankele, B., Klein, P., Kessel, S., and Weber, W.: Device Reliability in Analog CMOS Applications, IEEE International Electron Devices Meeting (IEDM), Technical Digest, 81–84, 1999. C., Brederlow, R., Ankele, B., Lill, A., Goser, K., and Thewes, R.: On the Degradation of P-MOSFETs in Analog and RF Circuits under Inhomogenous Negative Bias Temperature Stress, IEEE International Reliability Physics Symposium (IRPS), Proceedings, 5–10, 2003. T., Schlunder, C., Hommel, M., and Schneider, J.: Practical Aspects of Reliability Analysis for IC Designs”, 43rd Design Automation Conference, San Francisco, California, 24–28 July, 193–198, 2006
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