Threshold Voltage Degradation Research Articles

Parameter Extraction of Extended Floating Gate Field-Effect Transistors (EGFETs): Estimating the Threshold Voltage, Series Resistance, and Mobility Degradation From I–V Measurements

Parameter Extraction of Extended Floating Gate Field-Effect Transistors (EGFETs): Estimating the Threshold Voltage, Series Resistance, and Mobility Degradation From <i>I</i>–<i>V</i> Measurements

Time-dependent statistical NBTI model for aging assessment in circuit level implemented with open model interface

As technology nodes continue to shrink, the impact of aging problems on devices has become increasingly important. One significant aging problem that affects device characteristics and circuit performance is Negative Bias Temperature Instability (NBTI). Under small-size conditions, fluctuations in device parameters such as threshold voltage due to aging are not negligible. To capture these fluctuations, an improved statistical model has been proposed. The time-dependent statistical model accounts for the average change in the number of charged defects due to NBTI and enables the evaluation of degradation fluctuations over time. The model prediction of the threshold voltage degradation of devices in advanced technology is verified with different measured data. Furthermore, the model is implemented with the Open Model Interface (OMI) for the circuit-level degradation simulation, taking advantage of OMI's convenience and compatibility with different circuit simulators. The integration of the proposed model into the OMI benefits in predicting the degradations difference among the transistors in the circuits, reducing the overestimation of aging degradation compared to the methods that assume every transistor experiences the same and worst degradation.

AC-Stress Degradation in SiC MOSFETs

This work presents very recent results regarding threshold-voltage (VT) degradation due to the application of an AC gate-bias stress (also known as a gate-switching stress). We show that this phenomenon includes both a seemingly-permanent VT shift and an increase in the observed VT hysteresis. This degradation effect is found primarily in trench-geometry devices when exposed to what can be described as a negative bias overstress that exceeds the negative bias rating of the device, but that not all trench devices are equally susceptible, suggesting that device design and processing details are critical in limiting the severity of this effect.

Demonstration of β-Ga2O3 nonvolatile flash memory for oxide electronics

This report demonstrates an ultrawide bandgap β-Ga2O3 flash memory for the first time. The flash memory device realized on heteroepitaxial β-Ga2O3 film had TiN as the floating gate (FG) and Al2O3 as tunneling and gate oxides. A memory window of > 4 V was obtained between the programmed and erased states of the device. The memory states showed negligible degradation in threshold voltage (VTH) even after 5000 s, exhibiting excellent nonvolatility. Furthermore, the device showed a VTH of ∼0.3 V after applying a 17 V programming voltage pulse, indicating the potential of the electron trapping phenomenon in the FG to achieve enhancement-mode operation in β-Ga2O3 transistors for high-power and logic applications. This study would provide insights for future oxide electronics integrating β-Ga2O3 memory.

An Investigation of SILC Degradation under Constant Voltage Stress in PDSOI Devices.

The stress-induced leakage current (SILC) degradation of partially depleted silicon in insulator (PDSOI) devices under constant voltage stress (CVS) was studied. Firstly, the behaviors of threshold voltage degradation and SILC degradation of H-gate PDSOI devices under constant voltage stress were studied. It was found that both the threshold voltage degradation and SILC degradation of the device are power functions of the stress time, and the linear behavior between SILC degradation and threshold voltage degradation is good. Secondly, the soft breakdown characteristics of the PDSOI devices were studied under CVS. Thirdly, the effects of different gate stresses and different channel lengths on the threshold voltage degradation and SILC degradation of the device were studied. The results showed SILC degradation of the device under positive CVS and SILC degradation of the device under negative CVS. The shorter the channel length of the device was, the greater the SILC degradation of the device was. Finally, the influence of the floating effect on the SILC degradation of the PDSOI devices was studied, and the experimental results showed that the degree of SILC degradation of the floating device was greater than that of the H-type grid body contact PDSOI device. This showed that the floating body effect can exacerbate the SILC degradation of PDSOI devices.

산화물 박막 소자의 단기 열화 특성 분석 및 예측식 모델링

Gate bias stress can change the threshold voltage of amorphous indium gallium zinc oxide (a-IGZO) thin-film transistor (TFT). Especially, short-term degradation of threshold voltage should be compensated since it causes motion artifacts in the display. Therefore, a new short-term degradation model was proposed based on the stretched-exponential model. Moreover, the accuracy of the proposed model was confirmed by calculating the coefficient of determination between the measured data and the fitted data.

A multi-parameter fitting method based on matrix transformation for device aging modeling

This paper establishes an HCI (Hot Carrier Injection) aging model on NMOS device, focusing on the simultaneous degradation of multiple parameters (drain current in saturation region (Idsat) and threshold voltage (Vth)) in the process of extracting model parameters. In this paper, a matrix transformation method is used to convert the electrical parameters of device aging into SPICE model parameters, so as to construct the multi-dimensional model of device aging. In addition, the impact of temperature (T) and device size on the model coefficients is considered to improve the precision of aging model. The approach proposed in this work could also be used to model other devices’ aging process.

Parameter Extraction of Extended Floating Gate Field Effect Transistors (EGFETs): Estimating the Threshold Voltage, Series Resistance, and Mobility Degradation From I-V Measurements

Parameter Extraction of Extended Floating Gate Field Effect Transistors (EGFETs): Estimating the Threshold Voltage, Series Resistance, and Mobility Degradation From I-V Measurements

(Digital Presentation) Instability of α-Si:H TFTs under Simultaneous Ultraviolet Light Illumination and Different Bias Stresses

The threshold voltage degradation and recovery phenomena of the α-Si:H TFTs stressed by DC or AC biases under with or without UV light illumination are investigated. For the negative DC bias stress, the threshold voltage shift of the stressed α-Si:H TFTs measured in the reverse sweep mode is smaller than that in the forward sweep mode, but the threshold voltage recovery is opposite, owing to the different increment of subthreshold swing of the α-Si:H TFTs after stressing. For the AC biases stresses, there are no significant difference of threshold voltage shift between the stressed α-Si:H TFTs measured by forward sweep and reverse sweep modes due to the less increment of subthreshold swing of the α-Si:H TFTs after stressing. There are more threshold voltage degradation but less recovery of the α-Si:H TFTs stressed by lower AC frequency with the higher negative bias in a cycle than those stressed by higher AC frequency.

High Pressure Deuterium Annealing for Improved Immunity Against Stress-Induced Threshold Voltage Degradation

We demonstrate that high pressure deuterium (HPD) annealing presents effective process knob to achieve excellent threshold voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{V}_{\mathrm{ TH}}$ </tex-math></inline-formula> ) stability and superb electrical performance of MOSFETs. While devices without HPD annealing show significant negative shift in <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{V}_{\mathrm{ TH}}$ </tex-math></inline-formula> , the device with HPD annealing exhibits excellent <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{V}_{\mathrm{ TH}}$ </tex-math></inline-formula> stability under identical bias stress conditions. Due to the superior interface quality provided by HPD annealing, we achieve much lower SS and higher on-current along with negligible <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{V}_{\mathrm{ TH}}$ </tex-math></inline-formula> shift, which is desirable for multi-threshold and high-performance logic device.

AC-Stress Degradation and Its Anneal in SiC MOSFETs

Several important aspects related to the phenomena of ac gate-bias stress-induced threshold-voltage degradation in SiC MOSFETs are presented. These include a detailed investigation of the particular sensitivity of trench-geometry devices when exposed to a negative gate-bias overstress, the specific conditions that drive this degradation, and its recovery by the application of a dc negative bias temperature stress.

Fluorine-plasma treated AlGaN/GaN high electronic mobility transistors under off-state overdrive stress

Influences of off-state overdrive stress on the fluorine-plasma treated AlGaN/GaN high-electronic mobility transistors (HEMTs) are experimentally investigated. It is observed that the reverse leakage current between the gate and source decreases after the off-state stress, whereas the current between the gate and drain increases. By analyzing those changes of the reverse currents based on the Frenkel–Poole model, we realize that the ionization of fluorine ions occurs during the off-state stress. Furthermore, threshold voltage degradation is also observed after the off-state stress, but the degradations of AlGaN/GaN HEMTs treated with different F-plasma RF powers are different. By comparing the differences between those devices, we find that the F-ions incorporated in the GaN buffer layer play an important role in averting degradation. Lastly, suggestions to obtain a more stable fluorine-plasma treated AlGaN/GaN HEMT are put forwarded.

Analysis of DC Characteristics in PDSOI pMOSFETs Under the Combined Effect of NBTI and TID

The influence of DC characteristics in PDSOI pMOSFETs under different NBTI and TID conditions was investigated. The threshold voltage, trans-conductance, and subthreshold swing of the devices were compared before and after irradiation under NBTI conditions, and the lifetime of the devices was predicted. The contributions of interface-trap charges and oxide-trap charges to the threshold voltage degradation were analyzed under the combined effect of TID and NBTI. Based on the R-D model, the degradation of device parameters under the combined effect of TID and NBTI was explained in this paper.

Optimal read voltages decision scheme eliminating read retry operations for 3D NAND flash memories

Read error increment due to threshold voltage degradation is one of the primary reliability issues of 3D NAND flash memories. Read retry technique which reduces read errors by determining the optimal read voltages (ORVs) is an effective means to solve the problem. However, the extra read operations required by read retry increase the read latency in data read and recovery process. Here, we proposed an ORVs decision scheme without specific read retry operations (ORVD-WRRO) to eliminate the read operations required by read retry and thus decrease the read latency. ORVD-WRRO uses the proposed overlap-error-record error-correcting-code (OER-ECC) to determine the ORVs. Besides, ORVD-WRRO adds ORVs decision and modification operations between read sensing operations and the previous read and decoded data by OER-ECC can be used to determine the subsequent ORVs. Thus, the ORVs of the NAND flash memory can be determined without any extra read operations addition. Experimental results show that the deviations between ORVs determined by the proposed ORVD-WRRO and the true value of the ORVs is smaller than 44 mV and the raw bit error rate (RBER) is reduced to less than 0.0087 which is within the error correction capability of QC-LDPC(8255, 8890). Moreover, the proposed scheme can reduce the read and data recovery latency by 23.21% compared with the conventional scheme.

Comparison of Total Ionizing Dose Effects in SOI FinFETs Between Room and High Temperature

The synergetic effects of total ionization dose and high-temperature stress of SOI FinFETs are investigated under ON-state bias condition. The experiments and TCAD simulations are employed to analyze the influence of different trapped-charges in the gate and buried oxide on the threshold voltage and mobility variations on the ON-state current of the devices. Results show that the threshold voltage degradation worsens for n-SOI FinFETs but weakens for the p-SOI FinFETs. Also, the ON-state current of n-SOI FinFETs is significantly enhanced while the change of p-SOI FinFETs is weak under the synergetic effects. The threshold voltage degradation induced by synergetic effects for both n- and p-type SOI FinFETs can exceed the linear superposition of the two types of stresses, which may be related to the thermal release of trapped charges in the gate oxide. The enhanced degradation in the n-SOI FinFETs compared with the p-SOI FinFETs may result from the shallow energy level electron traps in HfO2. Besides, for both n- and p-type SOI FinFETs, the ON-state current variations under the synergetic effects depend on the competitive process of threshold voltage variation and the mobility fluctuation.

Investigating two-stage degradation of threshold voltage induced by off-state stress in AlGaN/GaN HEMTs

In this work, a two-step degradation phenomenon in D-mode Si3N4/AlGaN/GaN metal–insulator–semiconductor-high electron mobility transistors is discussed systematically. During off-state stress, threshold voltage shifts positively for a short duration, and is followed by a negative shift. In contrast, the off-state leakage continues to decrease throughout the entire stress. Results of varied measurement conditions indicate that carrier trapping at different regions dominates this phenomenon. It is interesting that under a large lateral electric field, electron–hole pairs are generated and will then be trapped at the gate dielectric layer. Furthermore, when increasing the stress temperature, impact ionization due to carriers from the gate electrode becomes more severe. Finally, devices with different gate insulator thicknesses are performed to verify the physical model of the degradation behavior.

Lateral profiling of gate dielectric damage by off-state stress and positive-bias temperature instability

Gate dielectric degradation caused by off-state stress (OSS) and positive-bias temperature instability (PBTI) was analyzed in terms of charge trapping inside the gate dielectric and at the interface. Under the same degree of stress voltage, the OSS damage caused more degradation of threshold voltage (VT) than the PBTI damage. When the two stresses were alternately applied to an n-channel MOSFET, they effectively produced a leftward shift in the VT. This was because a greater negative VT shift was produced by the OSS and a less positive VT shift was produced by the PBTI. By analyzing the characteristics of the gate induced drain leakage (GIDL), it was determined that charge trapping inside the gate dielectric was more localized on the drain side than on the source side after OSS, but was distributed at a relatively similar level along the channel length direction after PBTI. To analyze the interface traps caused by OSS and PBTI, charge pumping (CP) measurements were conducted to map their lateral distribution along the channel direction. The PBTI-induced interface traps were found to be symmetrically distributed on the source side and drain side, while the OSS-induced interface traps were more concentrated toward the drain side.

Three-point I–V spectroscopy deconvolves region-specific degradations in LDMOS transistors

Unlike traditional logic transistors, hot carrier degradation (HCD) in power transistors involves simultaneous and potentially correlated degradation in multiple regions. One must deconvolve and characterize the voltage- and temperature-dependence of these region-specific degradations to develop a predictive HCD model of power transistors. Unfortunately, power transistors' doping and geometrical complexities make it challenging to use traditional defect-profiling techniques, such as charge-pumping or gated-diode methods. This Letter uses a physics-based tandem-FET model of an Laterally Diffused MOS (LDMOS) transistor to develop a “three-point I–V spectroscopy” technique that uses the time-evolution of three critical points of the measured I–V characteristics to extract mobility and threshold voltage degradations in the channel and drift regions. This innovative approach should generalize to other configurations of the LDMOS transistor as well.

Effects of non-fatal electrostatic discharge on the threshold voltage degradation in nano CMOS devices

Effects of non-fatal electrostatic discharge on the threshold voltage degradation in nano CMOS devices

Effects of Ionization and Displacement Damage in AlGaN/GaN HEMT Devices Caused by Various Heavy Ions

The electrical degradation in AlGaN/GaN high-electron-mobility transistors (HEMTs) is examined under irradiation with 7.6-MeV carbon (C), 20-MeV oxygen (O), and 30-MeV fluorine (F) ions in situ. To characterize the radiation damage in the HEMTs, the ionizing dose D <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">i</sub> , displacement dose D <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">d</sub> , and number of vacancies versus the chip depth in the devices have been calculated for heavy ions. As expected, in all three types of HEMTs, the output current decreases more than 30% and threshold voltage positive shifts after the irradiation fluence of 4×10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">12</sup> ions/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The performance degradation of AlGaN/GaN HEMTs is caused by radiation-induced charged defects. Based on calculation and experimental results, it is shown that the nonionizing energy loss (NIEL) method is not suitable for estimating the degradation of AlGaN/GaN HEMTs either considering gallium vacancy or considering both gallium vacancy and nitrogen vacancy. In the same displacement damage dose, the threshold voltage degradation rate depends on the type of incident particles and independent of the channel length. The damage caused by carbon ions is the smallest and the damage caused by fluoride ions is the largest.