Abstract
We demonstrate that high pressure deuterium (HPD) annealing presents effective process knob to achieve excellent threshold voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{V}_{\mathrm{ TH}}$ </tex-math></inline-formula> ) stability and superb electrical performance of MOSFETs. While devices without HPD annealing show significant negative shift in <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{V}_{\mathrm{ TH}}$ </tex-math></inline-formula> , the device with HPD annealing exhibits excellent <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{V}_{\mathrm{ TH}}$ </tex-math></inline-formula> stability under identical bias stress conditions. Due to the superior interface quality provided by HPD annealing, we achieve much lower SS and higher on-current along with negligible <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{V}_{\mathrm{ TH}}$ </tex-math></inline-formula> shift, which is desirable for multi-threshold and high-performance logic device.
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More From: IEEE Transactions on Device and Materials Reliability
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