Deep-submicrometer MOSFETs Research Articles

Compact Modeling of Drain Current Thermal Noise in FDSOI MOSFETs Including Back-Bias Effect

In this paper, we present an analytical charge-based model for thermal noise power spectral density in fully depleted silicon on insulator (FDSOI) MOSFETs. Two important aspects particular to FDSOI technology, namely, different inversion charges and different effective mobilities at front and back interfaces, are considered in the model. Proposed model is valid from weak to strong inversion regions of operation. Velocity saturation and channel length modulation are also incorporated to properly capture the excess noise in deep submicrometer MOSFETs. To test the quality of the model, standard benchmark tests are performed and asymptotic behavior of the model is validated in all regions of operation. The model is implemented in SPICE and validated with calibrated TCAD simulations as well as with experimental data of high frequency noise for wide range of back biases.

Quasi-2D Surface-Potential-Based Critical Length for Drift-Diffusion

The diffusive mobility $(\mu _{D})$ shifts toward ballistic mobility $(\mu _{B})$ dominant transport in deep submicrometer MOSFETs. The ballistic behavior is noticeable at much larger length scales in III-V-based devices. The transition between diffusive to ballistic mechanism is still not well modeled. In this letter, we present a physics-based model for the critical length $(\delta )$ derived from the quasi-2D solution of the 2D Poisson equation. The onset of ballistic behavior is better estimated from the $\delta $ rather than the channel length $(L)$ . The role of $\delta $ in determining the carrier transport mechanism in conceptual MOS devices is discussed. The presented model scales with the device electrostatics and can be used with the conventional compact models to get a smooth transition between different operating regimes due to channel-length scaling.

Effect of guard-ring on the DC and high-frequency performance of deep-submicrometer metal oxide semiconductor field effect transistor

The influence of guard-ring GR on the direct current DC and high-frequency performance of deep-submicrometer metal oxide semiconductor field effect transistors MOSFETs is investigated in this study. MOSFETs with four different GRs are fabricated using 90 nm complementary metal oxide semiconductor CMOS process, and a detailed comparative study on their device performances is performed. A united DC and small signal equivalent circuit model that takes into the effect of GR is developed. A set of simple, but efficient formulas provide a bidirectional bridge for the S parameters transformation between devices with different GRs. The corresponding model parameters for MOSFETs with different GRs are determined from S parameter on-wafer measurement up to 40 GHz. © 2013 Wiley Periodicals, Inc. Int J RF and Microwave CAE 24:259-267, 2014.

A compact model of fringing field induced parasitic capacitance for deep sub-micrometer MOSFETs

A compact model of fringing field induced parasitic capacitance has been developed. Geometrical parameters such as gate length, gate electrode thickness, oxide thickness and spacer thickness have been considered. By using proper conformal mapping method, we analytically modeled the capacitance between gate electrode and source/drain including metal electrode filled in the contact holes. We compared the model with the results of 2-D device simulation, and found very good agreement.

Comments on "A shield-based three-port de-embedding method for microwave on-wafer characterization of deep-submicrometer silicon MOSFETs"

Comments on "A shield-based three-port de-embedding method for microwave on-wafer characterization of deep-submicrometer silicon MOSFETs"

Author's reply [to comments on "A shield-based three-port de-embedding method for microwave on-wafer characterization of deep-submicrometer silicon MOSFETs"

For original article by Ming-Hsiang Cho et al. see ibid., vol.53, no.9, p.2926-34, Sep. 2005. For comments by T. Kaija and P. Heino see ibid., vol.54, no.3, p.1295-6, March 2006.

A shield-based three-port de-embedding method for microwave on-wafer characterization of deep-submicrometer silicon MOSFETs

A general three-port S-parameter de-embedding method using shield-based test structures for microwave on-wafer characterization is presented in this paper. This method does not require any physical equivalent-circuit assumption for the surrounding parasitics of a device-under-test. We use one open and three thru dummy devices to remove the parasitic components connected to the gate, drain, and source terminals of a MOSFET. By shielding the lossy silicon substrate, the cross-coupling from port to port can be significantly mitigated, and thus, the parasitics of probe pads and interconnects at each port can be separately subtracted. The MOS transistor and its corresponding dummy structures fabricated in a 0.18-/spl mu/m CMOS process were characterized up to 20 GHz. Compared with the two-port cascade-based de-embedding method, the proposed three-port de-embedding procedure can further eliminate the parasitics associated with the dangling leg in the source terminal. The impacts of the accuracy of the de-embedding technique on device modeling and simulation are also discussed.

Cascode Monolithic DC-DC Converter for Reliable Operation at High Input Voltages

A cascode bridge circuit for monolithic switching DC-DC converters operating at high input voltages is proposed in this paper. The proposed circuit can also be used as an I/O buffer to interface circuits operating at significantly different voltages. The circuit technique permits the full integration of the active and passive devices of a switching DC-DC converter with a high voltage conversion ratio in a standard low voltage CMOS technology. The cascode bridge structure guarantees the reliable operation of deep submicrometer MOSFETs without exposure to high voltage stress while operating at high input and output voltages. With the proposed circuit technique, steady-state voltage differences between the terminals of all of the MOSFETs in a switching DC-DC converter are maintained within a range imposed by a target low voltage CMOS technology. High-to-low DC-DC converters operating at input voltages up to three times as high as the maximum voltage that can be directly applied across the terminals of a MOSFET are described. An efficiency of 79.6% is achieved for 5.4 volts to 0.9 volts conversion assuming a 0.18 ?m CMOS technology. The DC-DC converter operates at a switching frequency of 97 MHz while supplying a DC current of 250 mA to the load.

An experimental study of carrier heating on channel noise in deep-submicrometer NMOSFETs via body bias

In this paper, RF noise in 0.18-/spl mu/m NMOSFETs concerning the contribution of carrier heating and hot carrier effect is characterized and analyzed in detail via a novel approach that modulates the channel carrier heating and number of hot carriers using body bias. We confirm qualitatively a negligible role of hot carrier effect on the channel noise in deep-submicrometer MOSFETs. For a device under reverse body bias (V/sub b/), even though the increase in hot carrier population is clearly characterized by dc measurements, the device high-frequency noise is found to be irrelevant to the increase in the channel hot carriers. Experimental results show that the high-frequency noise is slightly reduced with the increase in |V/sub b/|, and can be qualitatively explained by secondary effects such as the suppression of nonequilibrium channel noise and substrate induced noise. The reduction of NF/sub min/ and R/sub n/ with the increase in |V/sub b/| may provide a possible methodology to finely adjust the device high-frequency noise performance for circuit design.

Impact of Downscaling on High-Frequency Noise Performance of Bulk and SOI MOSFETs

Parameters limiting the improvement of high-frequency noise characteristics for deep-submicrometer MOSFETs with the downscaling process of the channel gate length are analyzed experimentally and analytically. It is demonstrated that the intrinsic Pucel's noise P, R, and C parameters are not strongly modified by the device scaling. The limitation of the noise performance versus the downscaling process is mainly related to the frequency performance (f/sub max/) of the device. It is demonstrated that for MOSFETs with optimized source, drain, and gate accesses, the degradation of the maximum oscillation frequency is mainly related to the increase of the parasitic feedback gate-to-drain capacitance and output conductance with the physical channel length reduction. Optimization of these internal parameters is needed to further improve the high-frequency noise performance of ultra deep-submicrometer MOSFETs.

Modeling of Statistical Low-Frequency Noise of Deep-Submicrometer MOSFETs

The low-frequency noise (LF-noise) of deep-submicrometer MOSFETs is experimentally studied with special emphasis on yield relevant parameter scattering. A novel modeling approach is developed which includes detailed consideration of statistical effects. The model is based on device physics parameters which cause statistical variations in LF-noise behavior of individual devices. Discrete quantities are used and analytical results for the statistical parameters are derived. Analytical equations for average value and standard deviation of noise power are provided. The model is compatible with standard compact models used for circuit simulation.

Improved extraction method for effective channel length of deep-submicrometre MOSFETs

An improved method for extracting the effective channel length in deep-submicrometre MOSFETs using S-parameter sets of real devices with different mask gate length is developed to overcome the drawbacks of a conventional low-frequency C-V method. This improved method is based on the accurate determination of the inversion channel capacitance using a new technique to remove parasitic overlap and fringe capacitances.

An analysis of small-signal substrate resistance effect in deep-submicrometer RF MOSFETs

Two different explanations of the S/sub 22/ kink phenomenon in deep-submicrometer RF MOSFETs have been reported: Hjelmgren and Litwin (see IEEE Trans. Electron Devices, vol.48, no.2, p.397-399, 2001) attributed the phenomenon to the substrate resistance, while Lu et al. (see ibid., vol.49, no.2, p.333-340, 2001) concluded that it results from the transconductance, or simply speaking, the size of the transistor. In this paper, we extend the dual-feedback circuit methodology for the three-terminal FET model proposed by Lu et al. into a more general four-terminal model in order to account for the influence of the substrate resistance. Our results show that, for a given MOSFET, either substrate resistance or transconductance may cause a kink in S/sub 22/. In addition to the single kink, which results from the above two factors, the double kinks, which appear when the substrate resistance of a MOSFET is within a middle range (approximately 10/sup 2/ to 10/sup 4/ /spl Omega/), can also be accounted for by our extended model. Experimental data representative of 0.25 /spl mu/m gate MOSFETs are adopted to verify our theory. Excellent agreement between theoretical values and experimental data has been found, which indicates our theory can successfully explain the S/sub 22/ kink phenomenon in deep-submicrometer RF MOSFETs.

Modeling of parasitic capacitances in deep submicrometer conventional and high-K dielectric MOS transistors

In deep submicrometer MOSFETs the device performance is limited by the parasitic capacitance and resistance. Hence a circuit model is needed to treat these effects correctly. In this work, we have developed circuit models for the parasitic capacitances in conventional and high-K gate dielectric MOS transistors by taking into account the presence of source/drain contact plugs. The accuracy of the model is tested by comparing the modeled results with the results obtained from three-dimensional (3-D) Monte-Carlo simulations and two-dimensional (2-D) device simulations over a wide range of channel length and oxide thickness. The model is also used to study the dependence of parasitic capacitance on gate length, gate electrode thickness, gate oxide thickness, gate dielectric constant, and spacer width.

Accounting for quantum effects and polysilicon depletion from weak to strong inversion in a charge-based design-oriented MOSFET model

This paper presents a simple, physics-based, and continuous model for the quantum effects and polydepletion in deep-submicrometer MOSFETs with very thin gate oxide thicknesses. This analytical design-oriented MOSFET model correctly predicts inversion and depletion charges, transcapacitances, and drain current, from weak to strong inversion and from nonsaturation to saturation. One single additional parameter is used for polysilicon doping concentration, while the quantum correction does not introduce any new parameter. Comparison to experimental data of deep-submicrometer technologies is provided, showing accurate fits both for I-V and C-V data. The model offers simple relationships among effective electrical parameters and physical device parameters, providing insight into the physical phenomena. This new model thereby supports device engineering, analog circuit design practice, as well as efficient circuit simulation.

A comprehensive study of indium implantation-induced damage in deep submicrometer nMOSFET: device characterization and damage assessment

The impact of indium channel implantation on the current-voltage characteristics, gate oxide breakdown and hot-carrier reliability of deep submicrometer nMOSFETs is studied in detail. A significantly faster oxide wear-out during ramped-voltage testing and a distinctly enhanced drain current degradation during hot-carrier stressing are observed in devices with implant dose ranging from 1-2 /spl times/ 10/sup 13/ cm/sup -2/. An important generation leakage is also measured in the long-channel MOSFET, although such irregularity is normally not detected in short-channel devices owing to predominant subthreshold current. The loss in device reliability may be attributed to the generation of local amorphous regions in the channel when the implant dose exceeds 10/sup 13/ cm/sup -2/. The limited thermal budget of the subsequent gate oxidation step is generally unable to anneal out these defects, which in turn lead to the formation of local weak spots and strained Si-H bonds in the gate oxide, and dislocation loops in the channel region. This finding raises an important concern on the use of indium implantation in retrograde channel engineering, since implant doses on the order of 10/sup 13/ cm/sup -2/ are often needed for effective suppression of short-channel effects. In order to minimize the loss in device reliability, the damaged lattice would need to be restored using a dedicated thermal annealing cycle prior to gate oxidation. A good correlation between the hot-carrier stress data and the DC current-voltage (DCIV) measurement data is also presented. This makes the DCIV technique a precise, nondestructive monitor for implantation-induced damage in deep submicrometer MOSFET, via a direct measurement of the process-residue interface traps.

RF noise in 0.18-μm and 0.13-μm MOSFETs

Studied the gate finger number and gate length dependence on minimum noise figure (NF <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">min</sub> ) in deep submicrometer MOSFETs. A lowest NF <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">min</sub> of 0.93 dB is measured in 0.18-μm MOSFET at 5.8 GHz as increasing finger number to 50 fingers, but increases abnormally when above 50. The scaling gate length to 0.13 μm shows larger NFmin than the 0.18-μm case at the same finger number. From the analysis of a well-calibrated device model, the abnormal finger number dependence is due to the combined effect of reducing gate resistance and increasing substrate loss as increasing finger number. The scaling to 0.13-μm MOSFET gives higher NF <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">min</sub> due to the higher gate resistance and a modified T-gate structure proposed to optimize the NF <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">min</sub> for further scaling down of the MOSFET.

A thermal activation view of low voltage impact ionization in MOSFETs

The authors present a thermal activation perspective for direct assessment of the low voltage impact ionization in deep-submicrometer MOSFETs. A comparison of the experimentally determined activation energy and a simple theoretical model is used to demonstrate the underlying mechanism responsible for impact ionization at low drain bias. The study indicates that the main driving force of impact ionization changes from the electric field to the lattice temperature with power-supply scaling below 1.2 V. This transition of driving force results in a linear relationship between log(I/sub SUB//I/sub D/) and V/sub D/ at sub-bandgap drain bias, as predicted by the proposed thermally-assisted impact ionization model.

Intrinsic threshold voltage fluctuations in decanano MOSFETs due to local oxide thickness variations

Intrinsic threshold voltage fluctuations introduced by local oxide thickness variations (OTVs) in deep submicrometer (decanano) MOSFETs are studied using three-dimensional (3-D) numerical simulations on a statistical scale. Quantum mechanical effects are included in the simulations employing the density gradient (DG) formalism. The random Si/SiO/sub 2/ and gate/SiO/sub 2/ interfaces are generated from a power spectrum corresponding to the autocorrelation function of the interface roughness. The impact on the intrinsic threshold voltage fluctuations of both the parameters used to reconstruct the random interface and the MOSFET design parameters are studied using carefully designed simulation experiments. The simulations show that intrinsic threshold voltage fluctuations induced by local OTV become significant when the dimensions of the devices become comparable to the correlation length of the interface. In MOSFETs with characteristic dimensions below 30 nm and conventional architecture, they are comparable to the threshold voltage fluctuations introduced by random discrete dopants.

Design and analysis of a new self-aligned asymmetric structure for deep sub-micrometer MOSFET

A new self-aligned asymmetric structure (SAAS) is proposed for deep sub-micrometer MOSFET and its device characteristics are analyzed. The proposed structure enables the source, drain and channel to be designed independently without additional lithography steps. SAAS with lateral asymmetric channel and highly doped source extension improves driving capability and short channel behavior without sacrificing hot carrier reliability. Based on the results of hydrodynamic device simulation over a wide range of process conditions, it is shown that highly doped asymmetric halo provides enhanced velocity overshoot and suppressed drain-induced barrier lowering. By employing asymmetric highly doped source extension, the degradation of driving capability is suppressed that can be caused by the increased parasitic resistance in highly doped asymmetric halo.