Deep Submicron Devices Research Articles

Novel gate and substrate triggering techniques for deep sub-micron ESD protection devices

As technology feature size is reduced, ESD becomes the dominant failure mode due to lower gate oxide breakdown voltage. In this paper, the effectiveness of new gate and substrate triggering techniques has been investigated to lower the trigger voltage of the LVTSCR and MOSFET based ESD protection circuits using 2D simulations and HBM/TLP measurements. The simulation results show that the using these techniques reduces the ESD triggering voltage by 63 and 44% for MOSFET-based and LVTSCR-based ESD structures, respectively, under 2kV HBM ESD stress. The effectiveness of proposed gate and substrate triggering techniques is also confirmed by the HBM and TLP measurements.

Deep Sub-Micron Device and Analog Circuit Parameter Sensitivity to Process Variations with Halo Doping and Its Effect on Circuit Linearity

Single halo (SH) and double halo (DH) metal oxide semiconductor field effect transistors (MOSFETs) have been reported to exhibit excellent short channel performance in the sub 100 nm regime. In this work, the effect of process variations such as gate oxide thickness, implantation parameters, channel length and temperature are systematically investigated on the device and analog circuit performance for all these technologies. Our simulation results on differential amplifiers and current mirrors show that, for an identical Vt mismatch in conventional (CON), DH, and SH devices, SH MOSFETs show a lower variation in the circuit parameters. It is found that, for a specified circuit parameter variation, almost a 25% higher Vt mismatch is tolerable with SH technologies as compared to the CON technologies. We also report in this work that, better saturation characteristics observed with SH devices improve the linearity of amplifiers when compared with the CON and DH devices, biased at identical voltage gains. However, one needs to account for the increased body bias induced non-linearity with SH technologies as demonstrated using circuit simulations for source follower and simple sample and hold circuits.

Substrate current, gate current and lifetime prediction of deep-submicron nMOS devices

Experimental results are presented to indicate that the widely used power-law models for lifetime estimation are questionable for deep-submicron (<0.25 μm) MOS devices, particularly for the case of large substrate current stressing. This observation is attributed to the presence of current components, such as the gate tunneling current and base current of parasitic bipolar transistor, that do not induce device degradation. A more effective extrapolation method is proposed as an alternative for the reliability characterization of deep-submicron MOS devices.

Epitaxial silicide formation on recoil-implanted substrates

An epitaxy-on-recoil-implanted-substrate (ERIS) technique is presented. A disordered surface layer, generated by forward recoil implantation of ∼0.7−3×1015cm−2 of oxygen during Ar plasma etching of surface oxide, is shown to facilitate the subsequent epitaxial growth of ∼25–35-nm-thick CoSi2 layers on Si(100). The dependence of the epitaxial fraction of the silicide on the recoil-implantation parameters is studied in detail. A reduction in the silicide reaction rate due to recoil-implanted oxygen is shown to be responsible for the observed epitaxial formation, similar to mechanisms previously observed for interlayer-mediated growth techniques. Oxygen is found to remain inside the fully reacted CoSi2 layer, likely in the form of oxide precipitates. The presence of these oxide precipitates, with only a minor effect on the sheet resistance of the silicide layer, has a surprisingly beneficial effect on the thermal stability of the silicide layers. The agglomeration of ERIS-grown silicide layers on polycrystalline Si is significantly suppressed, likely from a reduced diffusivity due to oxygen in the grain boundaries. The implications of the present technique for the processing of deep submicron devices are discussed.

A Study on the Electrical Characteristics of Ultra Thin Gate Oxide

Deep sub-micron device required to get the superior ultra thin gate oxide characteristics. In this research, I will recommend a novel shallow trench isolation structure(STI) for thin gate oxide and a <TEX>$N_2$</TEX>O gate oxide 30 <TEX>$\AA$</TEX> by NO ambient process. The local oxidation of silicon(LOCOS) isolation has been replaced by the shallow trench isolation which has less encroachment into the active device area. Also for <TEX>$N_2$</TEX>O gate oxide 30 <TEX>$\AA$</TEX>, ultra thin gate oxide 30 <TEX>$\AA$</TEX> was formed by using the <TEX>$N_2$</TEX>O gate oxide formation method on STI structure and LOCOS structure. For the metal electrode and junction, TiSi<TEX>$_2$</TEX> process was performed by RTP annealing at 850 <TEX>$^{\circ}C$</TEX> for 29 sec. In the viewpoints of the physical characteristics of MOS capacitor, STI structure was confirmed by SEM. STI structure was expected to minimize the oxide loss at the channel edge. Also, STI structure is considered to decrease the threshold voltage, result in a lower Ti/TiN resistance( Ω /cont.) and higher capacitance-gate voltage(C- V) that made the STI structure more effective. In terms of the TDDB(sec) characteristics, the STI structure showed the stable value of 25 % ～ 90 % more than 55 sec. In brief, analysis of the ultra thin gate oxide 30 <TEX>$\AA$</TEX> proved that STI isolation structure and salicidation process presented in this study. I could achieve improved electrical characteristics and reliability for deep submicron devices with 30 <TEX>$\AA$</TEX> <TEX>$N_2$</TEX>O gate oxide.

Strain mapping in deep sub-micron Si devices by convergent beam electron diffraction in the STEM

The principles of the convergent beam electron diffraction technique, which is a point-to-point method for local strain analysis of thin crystals in the transmission electron microscope, are briefly outlined. The availability in modern instruments of scanning attachments coupled with high-angle annular dark-field detectors (STEM/HAADF) has recently enabled the automatic acquisition of diffraction patterns in a large number of points, selected by digitally rastering the probe in a two dimensional region of the sample. As the components of the strain tensor can be calculated at each point, 2D strain mapping has thus become possible. An example of application of the technique to deep sub-micron shallow-trench isolation structures in silicon is reported.

Current aspects and future perspectives of high-density MRAM

Magnetoresistive random access memory (MRAM) is regarded as one of the leading candidates for universal memory [1] that will be commercialized in the foreseeable future. The figure of merits for MRAM technology includes non-volatility, high speed, high density, radiation hardness, and unlimited endurance. Very promising R & D results have been announced wordlwide. For a high density MRAM as a stand-alone memory, uniform resistance and switching control for sub-micron and deep sub-micron devices must be guaranteed. To achieve this goal, several material and device issues related with MRAM core cell should be resolved. Resistance (R) as well as magnetoresistance (MR) are limited by the uniformity of barrier thickness induced by bottom electrode. Switching issues appear controllable with a choice of appropriate shape and fine patterning process.

Electrical characteristics of ultra-thin gate oxides (

Ultra-thin gate oxides with thickness smaller than 3 nm were prepared by anodic oxidation (anodization) in deionized water under direct-current biasing superimposed with alternating-current signal (DAC-ANO). It is experimentally observed that the DAC-ANO oxides after suitable high temperature annealing have better electrical characteristics than conventional rapid thermal oxides (RTO). Other advantages of DAC-ANO oxides include lower leakage current, higher time-zero dielectric breakdown and time-dependent dielectric breakdown endurance, and less stress-induced leakage current. The charge trapping behavior under high field stress is less significant in DAC-ANO oxides than in RTO ones. The improved reliability of DAC-ANO oxides can be explained by the nature of AC switching effect. DAC-ANO oxide is a potential candidate in the application of ultra-thin gate oxide to deep sub-micron devices.

Modeling, testing, and analysis for delay defects and noise effects in deep submicron devices

The performance of deep submicron designs can be affected by various parametric variations, manufacturing defects, noise or modeling errors that are all statistical in nature. In this paper, we propose a methodology to capture the effects of these statistical variations on circuit performance. It incorporates statistical information into timing analysis to compute the performance sensitivity of internal signals subject to a given type of defect, noise or variation sources. Next, we propose a novel path and segment selection methodology for delay testing based on the results of statistical performance sensitivity analysis. The objective of path/segment selection is to identify a small set of paths and segments such that the delay tests for the selected paths/segments guarantee the detection of performance failure. We apply the proposed path selection technique for selection of a set of paths for dynamic timing analysis considering power supply noise effects. Our experimental results demonstrate the difference in estimated circuit performance for the case when power supply noise effects are considered versus when these effects are ignored. Thus, they indicate the need for considering power supply noise effects on delays during path selection and dynamic timing analysis.

Gate Depletion in WSix/Polysilicon Gate Stack and Effects of Phosphorus Ion Implantation

Systematic investigation of the gate depletion effects on the WSix/polysilicon gate stack has been performed. It was shown that decreasing the polysilicon thickness, gate oxide thickness, and phosphorus concentration of the polysilicon layer led to an increase in the gate depletion that degrades the drivability of metal–oxide–semiconductor field-effect transistors (MOSFETs). A furnace annealing process at high temperatures enhanced the gate depletion because the dopant atoms of polysilicon diffuse into the upper WSix layer. On the contrary, the rapid thermal annealing process seemed to suppress the gate depletion, but it produced a large number of interface states in the SiO2/silicon that required a conventional furnace re-annealing to remove. We found that phosphorus ion implantation in the WSix/polysilicon gate stack with activation annealing is a very effective method of minimizing the gate depletion effect, which can be utilized in fabricating deep sub-micron MOS devices.

Direct observation of secondary ionization current in n-channel MOSFETs

Hot-electron current in an n-channel MOSFET at high drain bias and on or off gate bias generates secondary currents amounting to a fraction of the primary (drain) current, in a surrounding n-well and the underlying p-substrate for a triple well device. Secondary current can also be collected in the source for the gate-off condition. The relative magnitude of these secondary currents is studied depending on MOSFET length and channel doping concentration. For a MOSFET with a heavy doping concentration in the channel near the drain junction, it is shown that a significant part of the secondary current is made of electrons originating from the space charge region of the drain, that escape the drain field and diffuse through the neutral substrate toward the source and surrounding n-well. These electrons are likely the product of secondary impact ionization by holes generated in the space-charge region of the drain. Similar secondary current is collected in the n-well surrounding a MOSFET in Fowler-Nordheim (FN) tunneling from the inversion layer to the gate. In this case, too, secondary electrons generated by holes returning from the oxide into the MOS channel appear to escape into the p-type body and flow to the surrounding n-well. These findings contradict the belief that secondary currents associated with hot carrier phenomena are only induced by hot carrier generated light, or secondary bipolar injection. Secondary ionization as a source of secondary current was rejected for older MOS devices. This paper shows experimentally and theoretically that secondary ionization and the ensuing hot carrier escape have become significant in today's deep submicron devices.

High- k dielectrics by UV photo-assisted chemical vapour deposition

An overview of our recent work on thin films of metal oxides deposited on silicon by a novel excimer lamp-assisted ultraviolet injection liquid source CVD (UVILS-CVD) process for advanced high- k gate dielectrics applications will be presented. Recent results on TiO 2, Ta 2O 5, ZrO 2, HfO 2, and TiO 2-doped Ta 2O 5 will be demonstrated. The physical, structural, surface and interfacial properties and electrical characterisation of the as-deposited and UV-annealed new high dielectric constant (high- k) materials, determined using ellipsometry, Fourier transform infrared spectroscopy, X-ray photoelectron spectroscopy, UV spectrophotometry, SEM, TEM and C– V, I– V measurements, showed that good quality layers could be produced. The investigation of high- k dielectrics grown by the UVILS-CVD process clearly demonstrates that low cost, high power density excimer lamp systems can provide an interesting alternative to conventional UV lamps and excimer lasers for industrial large-scale low temperature materials processing. UVILS-CVD is a promising technique for the controlled deposition of ultra-thin high- k metal-oxide dielectrics for deep sub-micron CMOS devices at temperatures as low as 350 °C.

Hydrodynamic modeling of short-channel devices using an upwind flux vector splitting scheme

Upwind flux vector splitting is presented for hydrodynamic modeling of 1D and 2D deep-submicron semiconductor devices. This approach splits the Jacobian matrices of the hydrodynamic system into two parts corresponding to forward and backward running fluxes, and an upwind difference is applied to each split flux. Influences of the boundary discontinuity of electric field and velocity on transport results in the 2D deep-submicron devices are discussed. The study demonstrates that the developed method is capable of handling large discontinuity of the boundary conditions, and highly non-linear source terms in short-channel semiconductor devices.

Channel engineering for analog device design in deep submicron CMOS technology for system on chip applications

Scaling of analog CMOS in the deep submicron regime is challenging, particularly for mixed mode system on chip applications due to the tradeoff in design requirements for analog and digital applications. The conventional approach employing aggressive gate oxide and S/D junction scaling to suppress the two-dimensional (2-D) electrostatic coupling and related short channel effects that degrade the device behavior in the deep submicron regime, though, improves the digital performance. However, this approach is not sufficient to obtain a reasonable analog performance. This paper presents a comprehensive study on the analog performance of scaled MOSFETs and explores alternative ways for improving the analog performance of these devices. It is shown that an easily integrable innovative channel engineering scheme in the form of single pocket structures can be used in the standard logic CMOS process to significantly improve the device analog performance of the deep submicron devices.

Series resistance calculation for source/drain extension regions using 2-D device simulation

Series resistance in the source/drain region is becoming a bottleneck for MOS device performance. A rigorous, simulation-based method for calculating resistance components that correctly accounts for current spreading is presented. Resistance calculation strategies used to project lateral abruptness requirements for future scaling, based on partitioning the device into vertical strips, are shown to cause substantial errors when current spreading occurs. This can result in an overestimate of the benefits of abrupt junctions. The physical resistances obtained from simulated devices are compared with the extracted resistances from the shift-and-ratio method. Discrepancies can be explained based on violation of the basic assumptions of the shift-and-ratio method: that series resistance is bias independent and the channel resistance is directly proportional to the channel length. A new extraction method that relaxes these assumptions is presented and used to provide deeper understanding in the application of the shift-and-ratio method to deep submicron devices.

Mapping of electrostatic potential in deep submicron CMOS devices by electron holography.

Quantitative two-dimensional maps of electrostatic potential in device structures are obtained using off-axis electron holography with a spatial resolution of 6 nm and a sensitivity of 0.17 V. Estimates of junction depth and variation in electrostatic potential obtained by electron holography, process simulation, and secondary ion mass spectroscopy show close agreement. Measurement artifacts due to sample charging and surface "dead layers" do not need to be considered provided that proper care is taken with sample preparation. The results demonstrate that electron holography could become an effective method for quantitative 2D analysis of dopant diffusion in deep-submicron devices.

Principles of transient charge pumping on partially depleted SOI MOSFETs

A new method to determine the interface trap density in partially depleted silicon-on-insulator (SOI) floating body MOSFETs is proposed for the first time. It can be considered as a "transient" charge-pumping (CP) technique in contrast to the normally used "steady-state" method. In our technique, majority carriers are removed from the floating body by applying a burst of pulses to the transistor gate. The change in the linear drain current after each pulse is used to determine the device interface trap density. The unique advantage of this method is the possibility to use it to characterize SOI MOSFETs without a body contact. The technique proposed is simple, reliable, and can be used for the characterization of deep submicron devices.

Potential fluctuations in metal–oxide–semiconductor field-effect transistors generated by random impurities in the depletion layer

We have studied the magnitude and length scale of potential fluctuations in the channel of metal–oxide–semiconductor field-effect transistors due to the random positions of ionized impurities in the depletion layer. These fluctuations effect the threshold voltage of deep submicron devices, impede their integration, and reduce yield and reliability. Our simple, analytic results complement numerical, atomistic simulations. The calculations are based on a model introduced by Brews to study fluctuations due to charges in the oxide. We find a typical standard deviation of 70 mV in the potential below threshold, where the channel is empty, falling to 40 mV above threshold due to screening by carriers in the channel. These figures can be reduced by a lightly doped epitaxial layer of a few nm thickness. The correlation function decays exponentially in an empty channel with a length scale of 9 nm, which screening by carriers reduces to about 5 nm. These calculations of the random potential provide a guide to fluctuations of the threshold voltage between devices because the length of the critical region in a well-scaled transistor near threshold is comparable to the correlation length of the fluctuations. The results agree reasonably well with atomistic simulations but detailed comparison is difficult because half of the total standard deviation comes from impurities within 1 nm of the silicon–oxide interface, which is a single layer of the grid used in the simulations.

Influence of the distribution function shape and the band structure on impact ionization modeling

Accurate modeling of impact ionization is a critical issue for deep submicron devices. All established analytical models for the distribution function based on the local electric field or on the local average carrier energy give rather poor results. Therefore, theoretically sound microscopic scattering rates cannot be properly transformed into accurate macroscopic models. We show that by accounting for the average square energy an accurate analytical description of the distribution function can be given. Together with a proper band structure model the analytical distribution function can then be used to evaluate microscopic models in a macroscopic device simulator. The present model is accurate for bulk and sub 100 nm feature size devices and involves only local quantities, which makes it a good choice for inclusion in conventional device simulators.

Strain Characterisation at the nm Scale of Deep Sub-Micron Devices by Convergent-Beam Electron Diffraction

Strain Characterisation at the nm Scale of Deep Sub-Micron Devices by Convergent-Beam Electron Diffraction