Gate Depletion in WSix/Polysilicon Gate Stack and Effects of Phosphorus Ion Implantation

Abstract

Systematic investigation of the gate depletion effects on the WSix/polysilicon gate stack has been performed. It was shown that decreasing the polysilicon thickness, gate oxide thickness, and phosphorus concentration of the polysilicon layer led to an increase in the gate depletion that degrades the drivability of metal–oxide–semiconductor field-effect transistors (MOSFETs). A furnace annealing process at high temperatures enhanced the gate depletion because the dopant atoms of polysilicon diffuse into the upper WSix layer. On the contrary, the rapid thermal annealing process seemed to suppress the gate depletion, but it produced a large number of interface states in the SiO2/silicon that required a conventional furnace re-annealing to remove. We found that phosphorus ion implantation in the WSix/polysilicon gate stack with activation annealing is a very effective method of minimizing the gate depletion effect, which can be utilized in fabricating deep sub-micron MOS devices.