Decimation Filter Research Articles

Improving Comb Aliasing Rejection Using Sharpening of Modified Comb

This paper presents an efficient method to improve the comb aliasing rejection in a comb decimation filter without increasing its passband droop. This problem is important since aliasing and comb passband droop may deteriorate the decimated signal. We propose here to apply sharpening of the modified comb in the second stage of a two-stage comb structure. The modified comb is obtained by decreasing the middle coefficient of the impulse response of the cascade of two combs by 1/2. The sharpening polynomial with the first order tangencies is used here. As a result, the comb folding bands, where the aliasing occur, become wider and with an increased attenuation in comparison with the original comb filter. However, this improvement in the folding bands did not result in an increased passband droop. The compensator from literature is used to further decrease passband droop. The method is illustrated with examples and compared with the original comb and the methods proposed in literature for increasing aliasing rejection.

Optimization Design of Non-Integer Decimation Filter for Compressing Satellite Synthetic Aperture Radar On-board Data

The on-board processor of satellite Synthetic Aperture Radar(SAR) digitizes the back-scattered echoes and transmits them to the ground. As satellite SAR image of various operating conditions including broadband and high resolution is required, an enormous amount of SAR data is generated. Decimation filter is used for data compression to improve the transmission efficiency of these data. Decimation filter is implemented with the FIR(Finite Impulse Response) filter and here, the decimation ratio and tap length are constrained by resource requirements of FPGA used for implementation. This paper suggests to use a non-integer ratio decimation filter in order to optimize the data transmission efficiency. Also, it proposes a filter design method that remarkably reduces the resource constraints of the FPGA in-use via applying a polyphase filter structure. The required resources for implementing the proposed filter is analysed in this paper.

Delayless polyphase implementation of filters in active noise control systems

In real-time implementation of active noise control filters, high sampling rate is sometimes preferred to reduce the delay in analog-to-digital converters or to reduce the risk of aliasing effect. A multi-rate structure is usually implemented with a polyphase structure to maintain a low sampling rate for the control filters to avoid the increase of real-time computational load. However, the use of decimation or interpolation filter will introduce additional delay, which can negatively affect the noise control performance. In the current work, a delayless implementation of polyphase structure is proposed where the original active noise control filter is first constrained to have sufficient attenuation at high frequencies in its design phase and is then decomposed into two multiplicative sub-filters, each of which involves a sufficiently high frequency attenuation. These two decomposed sub-filters can perform both noise control and decimation/interpolation without introducing additional delay in the polyphase structure. The proposed delayless approach can thus reduce the delay of a traditional multi-rate active noise control system and, in principle, can provide better active noise control performance. Moreover, if a single rate system is implemented at a high sampling rate, the proposed polyphase structure in filter implementation can effectively reduce the real-time computational load.

A 400 mV 160 nW/Ch Compact Energy Efficient ∆Σ Modulator for Multichannel Biopotential Signal Acquisition System.

Analog to digitalconverter circuit design for biomedical systems with multiple recording channels presents challenges in high density and very low power consumption. Passive integrator and loop-filter based delta-sigma modulators (DSMs) have been recently reported for ultra-low-power and highly energy-efficient data converters for multi-channel biopotential acquisition. However, these modulators rely on a very high oversampling ratio (OSR) to achieve the target resolution. Higher OSR leads to higher power consumption in the modulator and the digital low-pass and decimation filter succeeding the DSM. We present a low OSR passive integrator-based DSM in this work by relying on a duty-cycled resistor (DCR). DCR enables the realization of large time constants in the already passive loop-filter, with minimal area and overhead power consumption. This leads to design of DSMs that are highly area, power and energy-efficient, suitable for multi-channel biopotential recording systems. We demonstrate a second order, duty-cycled passive integrator based CTDSM in a 65 nm CMOS technology for a 10 kHz biopotential bandwidth. Measurement results show that the fabricated design achieves an SNDR/DR of 56.36/63.1 dB while consuming only 160 nW power with an OSR of 32 and occupies an area of 0.035 mm 2 with a state-of-the-art energy efficiency of 14.9 fJ/conv. In-vitro and in-vivo measurements are provided to further demonstrate the operation of the proposed DSM.

Decimation of Delta-Sigma-Modulated Signals Using a Low-Cost Microcontroller

varDelta varSigma analog-to-digital converters (ADCs) are largely used in sensor acquisition applications. In the last few years, standalone varDelta varSigma modulators have become increasingly available as off-the-shelf parts. To build a complete ADC, a standalone modulator has to be paired with some advanced elaboration unit, such as a field programmable gate array (FPGA) or a digital signal processor (DSP), which is needed for the implementation of the decimation filter. This work investigates the use of low-cost, general-purpose microcontrollers for the decimation of varDelta varSigma -modulated signals. The main challenge is given by the clock frequency of the modulator, which can be in the range of a few hbox {MHz}. The proposed technique deals with this limitation by employing two serial peripheral interface (SPI) modules in a time-interleaved configuration. This approach allows for continuous acquisition and elaboration of relatively high-speed, digital signals. The technique has been applied to a case study, and a data conversion system has been practically realized. The performance of the proposed filter is compared to that of a digital filter, present on board a commercial microcontroller, and the results of experimental tests are provided.

High speed low area decimation filter for hearing aid application

High speed low area decimation filter for hearing aid application

Efficient design of decimation filter using linear programming and its FPGA implementation

In this paper we present two-stage CIC (cascaded-integrator-comb) decimation filters with decimation factor M expressed as M = M1M2, where M1,M2∈Z+. The proposed decimator-I aims to minimize the pass-band droop using a cascade connection of Kaiser Hamming (KH) and Saramäki-Ritoniemi (SR) sharpening structures. The coefficients of second stage are determined using linear programming in MATLAB. The proposed CIC decimator-I when designed for various integer decimation factors on an average has a pass-band droop of −0.09 dB at the normalized frequency of 1/2 M and an average alias rejection of −44 dB at the normalized frequency of 3/2 M. Further, another decimator-II structure extends decimator-I to achieve an alias rejection of −87 dB and pass-band droop of −0.17 dB. The FPGA implementation of proposed designs has lower slice utilization and achieves higher maximum operating frequency than other existing competing designs. The performance of proposed decimation filters is confirmed using computer simulations in analog-to-digital converters (ADC) and sigma-delta (ΣΔ) modulators.

On the application of sensor authentication with intrinsic physical features to vehicle security

Cybersecurity in the automotive sector is becoming increasingly important as modern vehicles can be exposed to cybersecurity threats and regulatory fraud. Sensor identification and authentication is an important function in the vehicle life cycle. This paper proposes an alternative or complementary identification and authentication approach to cryptographic techniques based on the physical properties of the Hall sensor, which is commonly used in odometers and motion sensors. The application of different signal processing algorithms to an experimental dataset of 12 Hall sensors was evaluated. In particular, a dimensionality reduction with decimation filters was applied to improve the time efficiency of the identification and authentication process while achieving high identification accuracy (accuracy=95%) and high authentication accuracy. In addition, the results show that different transformations with different hyperparameters are able to generate a wide range of challenges and responses to support the authentication process.

Design and vlsi implementation of a decimation filter for hearing aid applications

Roughly 10% of the total common people experience some kind of hearing misfortune, yet just little level of this measurement utilize the portable amplifier. The shame related with wearing a portable amplifier, client disappointment with listening device execution, the expense and the battery life. Using computerized signal handling the advanced portable amplifier currently offers what the simple listening device can't offer. As of now low power VLSI design is more preferable in digital designs. More and more individuals around the globe experience the ill effects of hearing misfortunes. The expanding normal age and the developing populace are the principle explanations behind this. The pulverization channel utilized for portable amplifier is planned and executed both in MATLAB and Very High Speed Integrated Circuit Hardware Description Language. The obliteration channel is structured utilizing the circulated number-crunching multiplier in Very High Speed Integrated Circuit Hardware Description Language. Each computerized channel structure is reproduced utilizing Matlab and its total engineering is caught utilizing Simulink. The subsequent engineering is equipment productive and expends less force contrasted with traditional decoding channels. Contrasted with the decoding FIR-FIR engineering, the structured decoding channel design utilizing Comb-half band FIR-FIR adds to an equipment sparing and decreases the force scattering.

Merenje komponenti električne snage po standardu IEEE 1459-2010

In this paper, the design and implementation of a novel recursive method for the power measurement ac-cording to the IEEE Standard 1459-2010 have been described. The most important parts are adaptive band and low-pass FIR filters that extract fundamental and dc components, respectively. In addition, by using oversampling techniques and decimation filters, coefficient sensitivity problems of the large-order FIR comb cascade structure are overridden and the parameter estimation accuracy is improved. The symmetrical components are estimated through a transformation matrix of adaptive phase shifters. The effectiveness of the proposed techniques is demonstrated by simulation results.

A Novel Approach for Optimal Design of Sample Rate Conversion Filter Using Linear Optimization Technique

This paper presents a sample rate conversion filter for decimation with flat passband. The proposed linear programming optimization (LPO) technique improves the magnitude response of filter with least computational complexity. Computational complexity has been a major factor in selection of decimation filter. Simulation results indicate that the proposed filter shows passband droop less than 0.007 dB with 50.5% decrease in computational complexity. The proposed filter eliminates the need of compensator.

Design of comb-based decimation filter with low power consumption, increased alias rejection and decreased passband droop

This paper presents design of a low power comb-based decimation filter for decimation of 100. The proposed structure is composed of two stages. The first and second stages are decimated by 4 and 25, respectively. The first stage is a non-recursive structure composed of two cosine filters each decimated by 2. The second stage is a Cascaded-Integrator-Comb (CIC) structure, decimated by 25. Since CIC structure is moved to lower rate, we get a low power structure. The alias rejection is improved increasing the number of cascaded filters by 1 or 2, at second stage. The passband droop is decreased by introducing the compensator at lower rate, i.e. after downsampling by 100. The parameters of compensator are obtained using method of intervals.

Design of Two-Stage Comb-Based Decimation Filter with High Aliasing Rejection and Low Passband Droop

This paper presents a simple method for the design of comb-based decimation filter with a high aliasing rejection and low passband droop. The method is based on the application of the mathematical result on zeros of symmetric polynomials on the unit circle. The application of this result leads to the introduction of the four additional single zeros into comb folding bands, where aliasing occur. As a result, the folding bands become wider and the aliasing rejection is increased. The passband droop is compensated by a simple compensator who works at low rate. The comparisons with the most recent methods from literature confirmed the advantages of this proposal regarding magnitude responses and the required complexity.

A Single-Trim Switched Capacitor CMOS Bandgap Reference With a 3σ Inaccuracy of +0.02%, −0.12% for Battery-Monitoring Applications

This article presents a single-trim switched capacitor (SC) CMOS bandgap reference (BGR) for battery monitoring applications. For a single-temperature trimming, β-compensation and curvature correction techniques are employed to minimize non-proportional-to-absolute-temperature (PTAT) errors. In conjunction with these techniques, this article proposes dynamic element matching (DEM) techniques with low-pass filtering which employs the decimation filter of a delta-sigma analog-to-digital converter (ADC) in a digital domain. It achieves a further reduction of non-PTAT errors resulting from mismatches of the bias current, of the PNP transistor current gain ( β), and of the gain coefficient in the SC summing amplifier. The remaining PTAT errors are canceled out using a single room-temperature trimming. The bandgap circuit is implemented using vertical PNP transistors with a β of about 2.7 at 27 °C in a 0.18- μm CMOS process. The proposed SC BGR achieves a 3σ inaccuracy of +0.02%, -0.12% from -40 °C to 125 °C. From a 1.8-V supply voltage, it consumes 17 μA at 27 °C and occupies an active area of 0.38 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

Design Optimization of PMU Anti-Aliasing Filters using Taguchi Method

A Phasor Measurement Unit (PMU) is a monitoring device, which serves in checking the power system condition by measuring voltage and current phasors along with frequency at a particular node. The basic structure of PMU consists of Synchronization Unit, Measurement Unit and Data Transmission Unit. The Measurement Unit has three components: Anti-aliasing filters, Analog-to-Digital Converter and Phasor measurement Unit/ Processor. An anti-aliasing filter ensures that all the analog signals have the same phase shift and attenuation thus assuring that the phase angle differences and relative magnitudes of the different signals are unchanged. Anti-aliasing filters made up of an analog front end and a digital decimation filter are far more stable as far as aging and temperature variations are concerned. IEEE C37.118 standard stipulates that it is mandatory to use the filter for avoiding any aliasing errors. Out of various analog filters, the Butterworth has been preferred due to its flat response in pass-band as compared to other filters. In this work, it is attempted to design anti-aliasing filters to be used in PMUs. The design problem is formulated as an optimization task that is solved using the Taguchi method. The results show better performance in terms characteristics compared to the conventional filters. The designed filters may be employed as building blocks in modern PMUs.

Integrating Signals With High Sampling Rates for Transmission Line Protection in Digital Substations

Travelling wave based protection functions require significantly higher sampling rates than protection functions based on time-domain superimposed quantities or fundamental frequency phasors. Integrating these high sampling rates in digital substations leads to a significant increase of the communication load of process-level networks and causes high computational cost for centralized protection systems. This paper builds on a distributed signal processing approach, which allocates the filtering operations among standalone merging units (SAMU). In particular, the paper presents a decimation filter design to integrate signals with high sampling rates at the process-level. Thereby, signal sequences with high, medium and low sampling rates are provided according to the requirements of the respective protection function. The decimation filter structure is optimized with respect to time delay by the Remez exchange algorithm and with respect to computational cost by a multistage approach and a sparse filter design algorithm. In addition, the filter response is verified against the accuracy constraints defined in IEC 61869-6 and IEC 61869-13. The paper shows that it is feasible to distribute the filtering operations among SAMUs, while keeping the time delay below the maximum allowable processing delay of 2 ms.

Sigma-Delta ADC on SOI Technology for Working at High Temperatures

We consider the integrated circuit design and the measurement results of test crystals for the 12-bit sigma-delta analog-to-digital converter (ADC) based on 180 nm silicon-on-insulator (SOI) technology from X-FAB. The ADC processes input signals in the frequency range up to 100 kHz in the temperature range of –40…+175 °C with the supply voltage equal to 3.3 V and the modulator clock frequency equal to 10 MHz. The circuit consists of the 5-th order switched-capacitor low-pass pre-filter to limit the input signal spectrum, the cascade connection of the second order sigma-delta modulators, and the digital decimation filter to reduce the clock frequency by 48 times. The main blocks of cutoff filter and modulator are assembled according to the balanced scheme on integrators based on operational transconductance amplifiers with the unity gain bandwidth of 63 MHz. The dynamic element matching circuit is used to expand the dynamic range of converter. It reduces the level of nonlinear distortions in digital-to-analog converters in the feedback circuits of modulator. The value of the SINAD parameter is not worse than 68 dB for converting the signal with the differential amplitude equal to 500 mV at the frequency of 100 kHz.

Heuristic Analysis of CIC Filter Design for Next-Generation Wireless Applications

This paper describes a novel multistage CIC filter which plays a vital role in software-defined radio (SDR) applications. In order to operate the baseband signal, wireless networking standards demand different sample rates. As a result, sample rate conversion (SRC) turns out as a pivotal method of SDR. Thus, cascaded integrator comb (CIC) filter is a distinct kind of linear-phase FIR filter which can be used as a decimation filter for SRC operation. The architecture of this filter is multiplierless with low passband droop; hence, it requires less area in contrast to other decimation filters. In this brief, the fundamental structure of CIC filter is examined with various parallel prefix adders and also the significant parameters of the CIC filter for different adders are exemplified. The proposed CIC filter with various parallel prefix adders has been designed in Verilog HDL using Xilinx ISE 14.7 and implemented on Kintex7 FPGA. The schemed CIC filter design is compared with the traditional CIC filter in view of area, speed and power consumption. Based on the obtained results on Kintex7 FPGA, the CIC filter with Brent Kung adder outperforms in terms of LUTs by 41.67% and power by 34.78% compared with the classical CIC filter and among the CIC filters using other parallel prefix adders. The proposed CIC uses new polynomial method which provides 33.33% reduction in passband droop and 41.14% reduction in stopband ripple compared to the existing sharpened CIC.

High performance hardware design of compressor adder in DA based FIR filters for hearing aids

Hearing aid is an acoustic device which is worn by hearing loss people. To compensate the different types of hearing loss, it is necessary to selectively amplify sounds at required frequencies. The main aim of the hearing aid is to selectively remove the noise signal such that the processed sound matches ones audiogram. To achieve this, the decimation filter in hearing aids can be design using multiplier less architecture which should be able to adjust sound levels at arbitrary frequencies within a given spectrum. In hearing aids, decimation filter plays a key role. This paper presents a low complexity design of a digital finite impulse response (FIR) filter for digital hearing aid application. This paper proposed approximate 4:2 compressor adders in memory less DA based FIR filter architecture. In DA architecture the area of the ROM increases gradually when filter order is increased. Memory less DA is designed using compressor adders is a solution to decrease the power consumption and area of the FIR filters and makes the area and power reduction for hearing aid application. The proposed DA based FIR filter architecture is synthesized on 90 nm technology using Synapsis Application Specific Integrated circuit design compiler. The proposed architecture has 45% reduction in area delay product when distinguish with systolic architecture and 10% less ADP when compare with OBC DA architecture. The proposed design is also implemented Field Programmable Gate Array and the results shows that the proposed architecture has less slices than best existing designs. The proposed architecture is used in decimation filter of hearing aids applications using matlab simulink, which removes the unwanted signal.

An FPGA-based Direct Sampling and Digital Processing System for Wideband and Narrowband Radar Signal

This paper designs an integrated wideband and narrowband radar signal direct sampling and digital processing system based on FPGA. The system comprises a VPX case, a main board, a direct sampling board, a fiber board. It makes direct sampling of 1.8GHz-3.0GHz echo waves, with 3.2GHz sampling rate. The wideband and narrowband echo waves share the same ADC channel. After ADC sampling, both of wideband and narrowband data are exported to a mix-free digital quadrature demodulation module in FPGA. The narrowband data will be further processed by digital frequency down conversion. The wideband data will be further processed by digital de-chirp operation, with parallel DDS structure and multi-level decimation filters. Data rate of both the wideband and narrowband data after processing is decreased obviously. The designed sampling system cut down the analog radar signal processing operation, and decreases signal distortion. Besides, it integrated the reception, sampling and processing of wideband and narrowband signal, simplified the structure of radar system.