Abstract
Travelling wave based protection functions require significantly higher sampling rates than protection functions based on time-domain superimposed quantities or fundamental frequency phasors. Integrating these high sampling rates in digital substations leads to a significant increase of the communication load of process-level networks and causes high computational cost for centralized protection systems. This paper builds on a distributed signal processing approach, which allocates the filtering operations among standalone merging units (SAMU). In particular, the paper presents a decimation filter design to integrate signals with high sampling rates at the process-level. Thereby, signal sequences with high, medium and low sampling rates are provided according to the requirements of the respective protection function. The decimation filter structure is optimized with respect to time delay by the Remez exchange algorithm and with respect to computational cost by a multistage approach and a sparse filter design algorithm. In addition, the filter response is verified against the accuracy constraints defined in IEC 61869-6 and IEC 61869-13. The paper shows that it is feasible to distribute the filtering operations among SAMUs, while keeping the time delay below the maximum allowable processing delay of 2 ms.
Highlights
F UTURE electric power systems are expected to have a high degree of converter-interfaced energy sources, which will decrease the inertia in the system as well as the shortcircuit power due to limited overcurrent capabilities of the semiconductor devices [1]
Travelling wave (TW) based protection functions have been proposed for such low inertia systems with limited short-circuit power, since their fault detection time is significantly faster than the fundamental frequency-based protection functions’ [3]
This paper showed that a single sampling process can be used to provide signal sequences for protection applications with high, medium and low sampling rate requirements, while taking into account the accuracy constraints stated in IEC 61869-6 and in IEC 61869-13 and the maximum allowable processing delay stated in IEC 61869-9
Summary
F UTURE electric power systems are expected to have a high degree of converter-interfaced energy sources, which will decrease the inertia in the system as well as the shortcircuit power due to limited overcurrent capabilities of the semiconductor devices [1]. Pling rates on switched Ethernet-based networks leads to a significant increase of the communication load To mitigate these challenges, the authors of this paper have in [19], [20] proposed to compute the protection related signal features directly at the point of measurement in a device termed distributed signal processing unit (DSPU). It has been shown that the communication load can be reduced significantly by the DSPU approach [20] Another challenge that arises with the integration of signals with high sampling rates Fh is the increased computational cost due to digital signal processing (DSP), such as filtering. This is essential, since the chosen sampling rate needs to be compatible with the protection IED in a digital substation
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