DC Bias Stress Research Articles

Bottom-gate Poly-Si Thin Film Transistors Fabricated by Blue Laser Diode Annealing and Their Reliability Under DC and AC Bias Stresses

Bottom-gate Poly-Si Thin Film Transistors Fabricated by Blue Laser Diode Annealing and Their Reliability Under DC and AC Bias Stresses

(Digital Presentation) Instability of α-Si:H TFTs under Simultaneous Ultraviolet Light Illumination and Different Bias Stresses

Hydrogenated amorphous silicon thin-film transistors (α-Si:H TFTs ) are widely applied in liquid crystal displays (LCD). They can be used as not only the switching devices in the panel but also the scan driving circuit in the active-matrix liquid crystal displays (AMLCD), as well as large-area optical imaging sensor arrays. The α-Si:H could be deposited on the glass or plastic substrates at the low temperature, good uniformity in the large area, and the process is relatively mature, so it is still a competitive material. This study would investigate the deterioration of the α-Si:H TFTs under various bias stressing conditions with and without UV light.For the DC bias stress on the gate terminal, the electron trapping within the gate dielectric under positive bias would cause the threshold voltage (Vth) to shift to the positive direction, but the hole trapping under negative bias would cause the Vth to shift to the negative one. Furthermore, under the DC bias stress, the UV light illuminates the TFTs simultaneously, and the active layer of TFTs would generate additional electrons and holes, which would increase the trapping probability of charges and the amount of degradation and recovery. Both effects of the electron capture in the dielectric and defects creation in the channel would cause the Vth to shift to the positive direction, so the degradation of TFTs under positive bias stress is relatively serious. The increment of the subthreshold swing of TFTs under negative bias stress would be much larger than those under positive one, and the captured holes are easily released in the reverse sweeping mode, leading to the decrease of the drain current. Therefore, the amount of degradation and recovery of the TFTs under negative bias stress is relatively small in the reverse sweeping mode, because the energy barrier of holes is smaller than that of electrons in the interface of α-Si:H/SiNx.For the experiments of AC bias stress on the gate terminal with UV light illuminating simultaneously, the frequency of AC signal is fixed at 10 KHz. It could be found that the leakage current in the cut-off region under negative bias (-35 ~ 0 V) stress would increase with the stress time lasting, which shows that the holes are trapped within the gate dielectric closer to the active layer at the high frequency. These shallow positive trapped charges would attract the electrons to accumulate in the channel region, which causes the drain current to increase gradually. However, under bipolar bias (-17.5 ~ +17.5 V) stress, the charge trapping would first dominate the Vth degradation of TFTs, and then the defect states creation would gradually dominate the change of the Vth as the stress time increasing, which causes the Vth first to shift to the negative direction and then to positive one.For another experiments of AC bias stress on the gate terminal without UV light illumination, the frequencies of AC signals are fixed at 10 Hz and 10 KHz with different ranges of biasing voltages. It could be found that the Vth degradation of TFTs at different frequencies under the higher positive bias cycle (0 ~ +35 and -10 ~ +25 V) is not obviously different, mainly because the speed of electron’s accumulation and disappearance in the channel region could keep up with the switching speed of AC signals. However, it could be found that during the higher negative bias cycle(-35 ~ 0 and -25 ~ +10 V), the amount of change in the Vth at low frequency is relatively larger than that at high frequency, which is due to the RC delay effect of the n+α-Si:H layer on the holes under negative bias stress. To investigate the recovery behavior of TFTs, including the direction and amount of the Vth change in the resting time, we could know the dominating mechanism that leads to the TFT’s degradation. And the probably balanced AC bias stress condition is about -10 ~ +25 V. As the magnitude of negative biasing voltage increases, the holes capture within the gate dielectric would increase, and the drain current in the cut-off region also increases.Finally, the β parameter, in the formula of ΔVth= Atβ, is obtained by fitting the trends of ΔVth v.s. stress times. The value of β parameter would exhibits the influence of different mechanisms on the degradation of TFTs stressed by different bias conditions and with/without UV light illumination over the stressing time. And these results are consistent with above experimental data.

(Digital Presentation) Degradation and Recovery of Low Temperature Poly-Si Thin Film Transistors Under DC and AC Bias Stresses

The low temperature poly-Si thin-film transistors (LTPS TFTs) have been extensively applied in the AMLCD and AMOLED due to their high carrier’s mobility and driving currents, and the ability to integrate the driving circuits onto the same substrate. The main mechanisms causing the degradation of the LTPS TFTs under bias stress are: hot carrier effect and self-heating effect. In this study, the degradation and recovery phenomena of the LTPS TFTs stressed by the hot carrier effect conditions would be systematically investigated. The device structures used in this study are n-channel LTPS TFTs with different lengths of lightly doped drain (LDD).First, we simultaneously apply a small positive DC voltage, approximately the threshold voltage plus 1V (Vth+1= +3 V), to the gate terminal and a large positive DC voltage (+12 V) to the drain terminal of the LTPS TFTs with three different LDD’s lengths. These stressing conditions would cause the TFTs operated in the saturation region, so that the channel is pinched off. And the electrons would be accelerated by a large transverse electric field when they drift from the source terminal to the drain one. The energetic electrons would impact the lattices of the channel and the interface between the gate dielectric and the channel near the drain terminal, causing the defect states and electron-hole pair generation. Few of the carriers with enough energy to overcome the energy barrier of gate dielectric would be trapped by the defects in it. The hot carrier effect causes the degradation of the TFTs devices, including the decrease of ON current and carrier mobility and the increase of OFF current, but less degradation of the threshold voltage and subthreshold swing. After the bias stressing, the resting time is added to investigate the recovery phenomena. The difference in the amount of degradation and the location of defects would cause the different recovery ratio. After the end of bias stressing, all of the terminals are not applied with any voltages in the resting periods. The electrons and holes generated in the channel near the drain terminal would recombine, and the defect states generated by the hot carrier impact slightly reduce, which causes the recovery phenomena of the degraded transistors.Then, we apply a small AC voltage (0 ~ +3 V) to the gate terminal and a large positive DC voltage (+12 V) to the drain one at the same time. This mode of bias stressing conditions is closer to the real operating mode of the TFTs in the driving circuits. From the experimental data, it could be found that there is no significant difference in the degradation of the TFTs under different frequency of AC signals applied on the gate. But the recovery ratio tends to gradually increase as the frequency increasing.Finally, a small positive DC voltage (+3 V) is applied to the gate terminal, and a large AC voltage (0 ~ +12 V) to the drain one at the same time. From the experimental data, it could be found that with the increase of AC signal frequency, the degradation of the TFTs decreases, but the recovery ratio of the TFTs increases due to the reduction of the effective stressing time in one period. As compared to the results of all stressing conditions, the TFTs, both of the gate and drain terminals applied with DC voltages, exhibit the largest degradation ratio but the least recovery one. However, the TFTs, as the gate terminal applied with DC voltages and drain one with AC voltage, exhibit the less degradation ratio but the largest recovery one.

Impact of the Low Temperature Ohmic Contact Process on DC and Forward Gate Bias Stress Operation of GaN HEMT Devices

In AlGaN/GaN high electron mobility transistors (HEMTs), high temperature processes (such as ohmic annealing with >800°C value) could deform the crystal structure and induce trap states within the bulk and surface. Expanded defect densities cause crucial problems, such as threshold voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{V}_{\text {th}}$ </tex-math></inline-formula> ) instability, current collapse, and high leakages. In this work, a low temperature ohmic contact process (630°C, 10 minutes) is adopted with recess etch, and contact resistances <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$&lt; 0.1\Omega ~\cdot $ </tex-math></inline-formula> mm with low sheet resistances are achieved. The positive impact of this low thermal budget process on surface morphology, DC operation, long-term stability, and forward gate bias stress of the device is studied.

(Digital Presentation) Degradation and Recovery of Low Temperature Poly-Si Thin Film Transistors Under DC and AC Bias Stresses

The degradation and recovery phenomena of n-type LTPS TFTs stressed at hot carrier effect region under various bias conditions are investigated. The devices with longer LDD’s length demonstrate less degradation ratio but more recovery ratio, because of the lower transverse electric field. As the AC signals are applied to the gate terminal, the degradation of devices shows no significant dependence of AC signal frequency, but the recovery ratio displays the similar trends as AC signal frequency changing. However, as the AC signals are applied to the drain terminal, the degradation of devices shows very significant dependence of AC signal frequency. The higher the AC signal frequency is, the less degradation the devices show, but the recovery ratio displays the similar trends as AC signal frequency changing. From the results of all stressing conditions, the LTPS TFTs stressed with DC voltages exhibit the largest degradation ratio but almost the least recovery one.

(Digital Presentation) Instability of α-Si:H TFTs under Simultaneous Ultraviolet Light Illumination and Different Bias Stresses

The threshold voltage degradation and recovery phenomena of the α-Si:H TFTs stressed by DC or AC biases under with or without UV light illumination are investigated. For the negative DC bias stress, the threshold voltage shift of the stressed α-Si:H TFTs measured in the reverse sweep mode is smaller than that in the forward sweep mode, but the threshold voltage recovery is opposite, owing to the different increment of subthreshold swing of the α-Si:H TFTs after stressing. For the AC biases stresses, there are no significant difference of threshold voltage shift between the stressed α-Si:H TFTs measured by forward sweep and reverse sweep modes due to the less increment of subthreshold swing of the α-Si:H TFTs after stressing. There are more threshold voltage degradation but less recovery of the α-Si:H TFTs stressed by lower AC frequency with the higher negative bias in a cycle than those stressed by higher AC frequency.

Nanoscale capacitance-voltage profiling of DC bias induced stress on a high-κ/SiO2/Si gate stack

We investigate DC bias stress effects on a HfOx/SiO2/p-Si gate stack using time-resolved scanning nonlinear dielectric microscopy. Our microscopy permits localized capacitance-voltage profiling and deep level transient spectroscopy on a particular area stressed prior to the measurement. We observed the increase of interface defect density and the drastic changes of local capacitance-voltage characteristics on the stressed area. Our numerical simulations explain that both fixed charges and interface defect density increased by the DC bias stress and caused the change of local characteristics. Because local capacitance-voltage characteristics is particularly important in device performance, time-resolved scanning nonlinear dielectric microscopy will be useful for the evaluation of local stress effects on miniaturized Si devices such as bias temperature instability.

Modulation of resistive switching properties of non-stoichiometric WO3−x based asymmetric MIM structure by interface barrier modification

The impact of device operation condition and ambient moisture on the interface-type resistive switching (RS) characteristics of a non-stoichiometric polycrystalline tungsten oxide (WO3−x) based metal–insulator–metal device with an Au top electrode and a Pt bottom electrode has been investigated. The device exhibits rectification and stable bipolar RS characteristics without the need for any forming step, where the switching is primarily dominated by the Schottky type Au/WO3−x interface. DC conduction characteristics of the device have been investigated at different temperature, bias stress, and relative humidity conditions. Current conduction through the active layer has been found to be dominated by Schottky emission at low electric field and Poole–Frenkel emission at high electric field. An increase in current and a strong reduction in the rectification characteristic have been observed on subjecting the device to DC bias stress of appropriate polarity as well as increasing ambient moisture. Modification of the Schottky barrier due to defect redistribution when DC bias stress is applied and due to the dipoles induced at the Au/WO3−x interface by water molecules with increasing ambient moisture content have been discussed as a possible mechanism of the observed RS modulation.

Reliability Concerns due to Self-Heating effects in GaN HEMTs

Current collapse phenomenon that occurs in GaN HEMTs under a moderately large DC bias stress, poses serious problems for usage of GaN technology in high-power high-frequency applications from a reliability standpoint. Additional problem in these devices operated at high biases is the appearance of self-heating effects that degrade device characteristics and, as shown in this work further amplify the problem of current collapse by changing the device electrostatics.

Edge Termination With Enhanced Field-Limiting Rings Insensitive to Surface Charge for High-Voltage SiC Power Devices

An edge termination structure with enhanced field-limiting rings (enhanced FLRs) is proposed to stabilize the breakdown voltage against the surface charge. The pitches of the enhanced rings are designed to mitigate the electric field and expand the depletion layer, which leads to an improvement of the breakdown voltage. In addition, the enhanced FLR is insensitive to surface charge because the field plates completely cover the n− layer. Simulation results indicated that the enhanced FLR did not have any fluctuation of breakdown voltage against surface charge density from 0 to ${1}\times {10}^{{13}}\,\,\text {cm}^{{-}{2}}$ , whereas conventional structures did have fluctuation. To examine the validity of the concept, we fabricated a silicon carbide (SiC) merged p-i-n Schottky diode with the proposed structure. DC bias stress tests at 150 °C over 1000 h demonstrated the breakdown voltage stability of the enhanced FLR.

LRS retention fail based on joule heating effect in InGaZnO resistive-switching random access memory

This study reports the low-resistance state retention fail of InGaZnO resistive-switching random access memory (ReRAM) under constant DC bias stress conditions by Joule heating effect. There were the abrupt state changes of InGaZnO ReRAM devices with high voltage stress over 0.6 V because of thermal energy in conducting filament. In addition, SPICE simulation was conducted with verilog-A to verify this retention fail mechanism. We believe these results are potentially useful to the analysis on the retention fail properties of ReRAM devices as well as the system-level simulations with reliability-awareness.

DC bias electric field and stress dependence of piezoelectric parameters in lead zirconate titanate ceramics – Phenomenological approach

The piezoelectric material behavior, including loss mechanism, under external DC electric field and stress biases have been extensively studied in lead zirconate titanate ceramics. However, in order to achieve a better understanding of these effects, development of a comprehensive model is required. The purpose of this paper is to develop a phenomenological model to explain the nonlinear nature of piezoelectric parameters under DC bias electric field and stress. Therefore, the Landau-Devonshire energy function considering external biases was developed and accordingly the material properties were derived, based on first order approximation. In order to explain the compliance and piezoelectric constants change higher order elastic and electrostrictive terms were introduced into the Gibb's free energy function.Accordingly, thermodynamic theory parameters, including higher order parameters, of a soft PZT were measured and characterized based on inverse permittivity behavior near Curie temperature. Finally, the phenomenological model predictions of material property changes under DC bias electric field and compressive stress were compared with experimental data reported by our group. The proposed model succeeded to explain the material properties change under external biases. Furthermore, the effect of DC electric field and compressive stress on loss parameters were explained based on domain wall motion.

Two-step degradation of a-InGaZnO thin film transistors under DC bias stress

A unified explanation is proposed to consistently explain the two-step degradation of amorphous InGaZnO (a-IGZO) thin film transistors (TFTs) under DC positive bias temperature instability (PBTI) stress without or with different drain stress voltages (Vds). For PBTI stress without stress Vds, this initial negative Vth shift is believed to be induced by donor-like defect states corresponding to H2O molecule and intrinsic defects, while for PBTI stress with stress Vds, the negative shift is believed to be induced by donor-like defect states corresponding to oxygen vacancies. The gate-bias-induced electron trapping mechanism is responsible for positive Vth shift. These transitions from negative to positive Vth shift are resulted from the competition between the donor-like states creation and electron trapping.

Top-gate organic field-effect transistors fabricated on paper with high operational stability

We report on top-gate organic field-effect transistors (OFETs) fabricated on specialty paper, PowerCoat™ HD 230 from Arjowiggins Creative Papers coated with a buffer layer composed of a polyvinyl alcohol (PVA) and polyvinylpyrrolidine (PVP) blend. OFETs operate at low voltages and display average carrier mobility values of 1.7 ± 1.1 × 10−1 cm2/Vs, average threshold voltage values of −1.4 ± 0.2 V, and average on/off current ratio of 105. OFETs also display excellent operational stability demonstrated by stable 1000 scans of the transfer characteristics and by stable on-currents displaying less than 6% change during a DC bias stress test at VDS = VGS = −10 V for 1 h. Furthermore, OFETs on paper display a decrease of only 7% in their on-state current during a bending test. The performance of these OFETs on paper is comparable to that displayed by top-gate OFETs with the same geometry fabricated on glass substrates.

Stretched-Exponential Trends in a-Igzo Tfts

A bias temperature stress (BTS) investigation of amorphous InGaZnO thin-film transistors (a-IGZO TFTs) is undertaken using the stretched-exponential (SE) relation to model the threshold voltage shift (ΔVTH) as a function of time, temperature, and applied gate voltage. Explicitly, the SE equation employed herein is described as ΔVTH (t, T, VG) = (VG-VTH0) (1-exp(-(t/τ)β)), where VTH0 is the initial unstressed TFT threshold voltage, τ is a trapping time, τ = τ0exp(Eτ/kBT), where τ0 is a trapping time prefactor, Eτ is an energy barrier, and β is an energy barrier parameter [1, 2]. Simulation indicates that a larger τ and/or β results in less ΔVTH, i.e., a more stable a-IGZO TFT. An alternate form of the SE voltage prefactor (VG-VTH0) involves the use of V0, which is identified as a saturation voltage [3, 4]. Either prefactor formulation can be used to accurately fit ΔVTH trends for stress times less than ~3 hours. However, as shown in Fig. 1, fitting of a sample data set restricted to stress times less than 3 hours leads to dramatically different saturated threshold voltage shifts, even though both prefactors precisely fit the initial 2 hours of data (see insert of Fig. 1). Physically, this is associated with the fact that the (VG-VTH0) prefactor corresponds to the applied overvoltage which explicitly depends on VG, while V0 is independent of VG. Simulation is useful for revealing various kinds of ΔVTH (t, T, VG) trends. For example, Fig. 2(a) shows that the relevant energy barrier, Eτ, associated with ΔVTH (10-5 s, 300 K, VG = 30 V) is very narrow for β = 1 and broadens dramatically as β → 0. The Eτ-β relationship is better represented by taking the derivative of ΔVTH with respect to Eτ, as shown in Fig. 2(b), where the magnitude of the peak increases and the distribution of Eτ narrows as β increases. As a larger β is indicative of a more stable TFT, it is reasonable to theorize that a narrow Eτ distribution is meaningful in predicting stable long-term TFT reliability. [1] M. Mativenga, et al., “High stable amorphous indium-gallium-zinc-oxide thin-film transistor using an etch-stopper and a via-hole structure,” Journal of Information Display, Vol. 12, No. 1, 47-50 (2011)[2] T. Y. Hsieh, et al., “Investigating degradation behavior of InGaZnO thin-film transistors induced by charge-trapping effect under DC and AC gate bias stress,” Thin Solid Films, 528, 53-56 (2013)[3] J. M. Lee, et al., “Bias-stress-induced stretched-exponential time dependence of threshold voltage shift in InGaZnO thin film transistors,” Applied Physics Letters, 93, 093304 (2008)[4] S. Park, et al., “Threshold voltage shift prediction for gate bias stress on amorphous InGaZnO thin film transistors,” Microelectronics Reliability, 52, 2215-2219 (2012) Figure 1

Initial time-dependent current growth phenomenon in n-type organic transistors induced by interfacial dipole effects

We describe an unusual phenomenon of time-dependent current growth in organic transistors, particularly n-type transistors. For an organic transistor based on N,N-ditridecyl-3,4,9,10-perylene tetracarboxylic diimide with a polyimide dielectric layer, the time-dependent increase in the drain current and an approximately hysteresis-free electricity were obtained under dc-bias stress. These phenomena could be attributed to (a) reduction in the trap-state density located at the interface between polyimide and semiconductor, (b) gate field effect enhanced by electric dipoles within polyimide, and (c) a low interface trap lifetime. This study reveals that polymer dielectrics with moderate polar groups are suitable for application in stable organic devices.

Low bias stress and reduced operating voltage in SnCl2Pc based n-type organic field-effect transistors

Vacuum deposited tin (IV) phthalocyanine dichloride (SnCl2Pc) field-effect transistors were fabricated on polymethylmethacrylate/aluminum oxide (PMMA/Al2O3) bilayer gate dielectric, with reduced operating voltage and low contact resistance. The devices with top contact Ag electrodes exhibit excellent n-channel behavior with electron mobility values of 0.01 cm2/Vs, low threshold voltages ∼4 V, current on/off ratio ∼104 with an operating voltage of 10 V. Bias stress instability effects are investigated during long term operation using thin film devices under vacuum. We find that the amount of bias stress of SnCl2Pc based thin film transistor is extremely small with characteristic relaxation time &amp;gt;105 s obtained using stretched exponential model. Stressing the SnCl2Pc devices by applying 10 V to the gate for half an hour results in a decrease of the source drain current, IDS of only ∼10% under low vacuum. These devices show highly stable electrical behavior under multiple scans and low threshold voltage instability under electrical dc bias stress (VDS = VGS = 10 V, for 2 h) even after 40 days.

Improved photovoltaic performance of crystalline-Si/organic Schottky junction solar cells using ferroelectric polymers

The effect of inserting an ultrathin layer of ferroelectric (FE) poly(vinylidene fluoride-tetrafluoroethylene) P(VDF-TeFE) at the crystalline (c-)Si/poly(3,4-ethylenedioxythiophene): poly(styrenesulfonate) (PEDOT:PSS) interface of a c-Si/PEDOT:PSS Schottky junction solar cell is demonstrated. P(VDF-TeFE) is a highly resistive material that exhibits a large, permanent, internal polarization electric field by poling of molecular dipole among the polymer chains. Because of these properties, performance can be enhanced by adjusting the thickness of the FE layer and subsequent poling process. Inserting a 3-nm-thick FE layer increases the power conversion efficiency η from 10.2% to 11.4% with a short-circuit current density Jsc of 28.85 mA/cm2, an open-circuit voltage Voc of 0.57 V, and a fill factor FF of 0.692. Subsequent poling of the FE layer under a reverse DC bias stress increased η up to 12.3% with a Jsc of 29.7 mA/cm2, a Voc of 0.58 V, and an FF of 0.71. The obtained results confirm that the spontaneous polarization of the FE layers is responsible for the enhancement of η, and that the polarization-based enhancement works if the FE layer is highly crystalline. These findings originate from efficient charge extraction to the electrodes and a suppression of non-radiative recombination at the c-Si/PEDOT:PSS interface.

(Invited) Instability Assessment and Modeling Of Amorphous InGaZnO Thin Film Transistors Under Alternating Pulse Bias Stresses

Amorphous InGaZnO (a-IGZO) TFTs have attracted more demands due to the transparency and high mobility. Since TFTs are always exposed to both positive and negative gate bias, the alternating DC bias stress tests are required to ensure stable TFT characteristics. Moreover, the analysis about scaling-down behavior under bias stress condition is required. In this paper, the effects of alternating pulse bias stress on the threshold voltage shift (ΔVth) of a-IGZO TFTs with respect to the stress time duration (t d) are analyzed by the variation of interface trap charges (Qit) and the channel electric field (E-field). In addition, the channel length-dependent tendency is verified using the concepts of the subgap density of states (DOS) and density of total trap states (NT).

WITHDRAWN: Investigating degradation behavior of InGaZnO thin-film transistors induced by charge-trapping effect under DC and AC gate bias stress

WITHDRAWN: Investigating degradation behavior of InGaZnO thin-film transistors induced by charge-trapping effect under DC and AC gate bias stress