Stretched-Exponential Trends in a-Igzo Tfts

Abstract

A bias temperature stress (BTS) investigation of amorphous InGaZnO thin-film transistors (a-IGZO TFTs) is undertaken using the stretched-exponential (SE) relation to model the threshold voltage shift (ΔVTH) as a function of time, temperature, and applied gate voltage. Explicitly, the SE equation employed herein is described as ΔVTH (t, T, VG) = (VG-VTH0) (1-exp(-(t/τ)β)), where VTH0 is the initial unstressed TFT threshold voltage, τ is a trapping time, τ = τ0exp(Eτ/kBT), where τ0 is a trapping time prefactor, Eτ is an energy barrier, and β is an energy barrier parameter [1, 2]. Simulation indicates that a larger τ and/or β results in less ΔVTH, i.e., a more stable a-IGZO TFT. An alternate form of the SE voltage prefactor (VG-VTH0) involves the use of V0, which is identified as a saturation voltage [3, 4]. Either prefactor formulation can be used to accurately fit ΔVTH trends for stress times less than ~3 hours. However, as shown in Fig. 1, fitting of a sample data set restricted to stress times less than 3 hours leads to dramatically different saturated threshold voltage shifts, even though both prefactors precisely fit the initial 2 hours of data (see insert of Fig. 1). Physically, this is associated with the fact that the (VG-VTH0) prefactor corresponds to the applied overvoltage which explicitly depends on VG, while V0 is independent of VG. Simulation is useful for revealing various kinds of ΔVTH (t, T, VG) trends. For example, Fig. 2(a) shows that the relevant energy barrier, Eτ, associated with ΔVTH (10-5 s, 300 K, VG = 30 V) is very narrow for β = 1 and broadens dramatically as β → 0. The Eτ-β relationship is better represented by taking the derivative of ΔVTH with respect to Eτ, as shown in Fig. 2(b), where the magnitude of the peak increases and the distribution of Eτ narrows as β increases. As a larger β is indicative of a more stable TFT, it is reasonable to theorize that a narrow Eτ distribution is meaningful in predicting stable long-term TFT reliability. [1] M. Mativenga, et al., “High stable amorphous indium-gallium-zinc-oxide thin-film transistor using an etch-stopper and a via-hole structure,” Journal of Information Display, Vol. 12, No. 1, 47-50 (2011)[2] T. Y. Hsieh, et al., “Investigating degradation behavior of InGaZnO thin-film transistors induced by charge-trapping effect under DC and AC gate bias stress,” Thin Solid Films, 528, 53-56 (2013)[3] J. M. Lee, et al., “Bias-stress-induced stretched-exponential time dependence of threshold voltage shift in InGaZnO thin film transistors,” Applied Physics Letters, 93, 093304 (2008)[4] S. Park, et al., “Threshold voltage shift prediction for gate bias stress on amorphous InGaZnO thin film transistors,” Microelectronics Reliability, 52, 2215-2219 (2012) Figure 1