DC-20 GHz Research Articles

Research on Low-Insertion-Loss Packaging Materials for DC-6 GHz Attenuation Chips

Research on Low-Insertion-Loss Packaging Materials for DC-6 GHz Attenuation Chips

A Wideband True Time Delay Circuit Using 0.25 µm GaN HEMT Technology.

This paper presents a wideband 4-bit true time delay IC using a 0.25 μm GaN HEMT (High-Electron-Mobility Transistor) process for the beam-squint-free phased array antennas. The true time delay IC is implemented with a switched path circuit topology using DPDT (Double Pole Double Throw) with no shunt transistor in the inter-stages to improve the bandwidth and SPDT (Single Pole Single Throw) switches at the input and the output ports. The delay lines are implemented with CLC π-networks with the lumped element to ensure a compact chip size. A negative voltage generator and an SPI controller are implemented in the PCB (Printed Circuit Board) due to the lack of digital control logic in GaN technology. A maximum time delay of ~182 ps with a time delay resolution of 10.5 ps is achieved at DC-6 GHz. The RMS (Root Mean Square) time delay and amplitude error are <5 ps and <0.6 dB, respectively. The measured insertion loss is <6.8 dB and the input and output return losses are >10 dB at DC-6 GHz. The current consumption is nearly zero with a 3.3 V supply. The chip size including pads is 2.45 × 1.75 mm2. To the authors' knowledge, this is the first demonstration of a true time delay IC using GaN HEMT technology.

A DC–20-GHz Impedance Tuner Using Power-Enhanced Stacked-FET Switch in 45-nm SOI CMOS

This letter presents the development of a dc–20 GHz impedance tuner in a 45-nm silicon-on-insulator complementary metal–oxide–semiconductor (CMOS) process. The proposed tuner consists of several short transmission line sections and tunable capacitors made up of small interdigital capacitors and switches. To increase the power handling capability, a switch topology using triple-stacked transistors and parallel capacitors is developed. The combination of the tuner architecture and the capacitor-switch arrangement enables the new tuner to have wideband operation, good tuning range, low loss, and high-power handling. The fabricated tuner can operate with RF power up to 27 dBm and provide a characteristic impedance tuning range from 56 to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$36~\Omega $ </tex-math></inline-formula> over dc–20-GHz bandwidth. In different operating states, the tuner demonstrates an insertion loss of 0.25–1.25 dB, an output 1-dB compression point (OP1dB) of better than 24 dBm, and an input third-order intercept point (IIP3) of better than 40 dBm.

Сверхширокополосный pin-диодный диплексерный переключатель на GaAs

The article presents a circuit of an ultra-wideband pin-diode switch for two channels with different operating frequency ranges: DC-18 GHz and 18–26.5 GHz. A topology model of a microwave monolithic integrated circuit (MMIC) based on quasi-vertical GaAs pin diode technology of Miсran JSC is described. Comparison of simulation results and experimental measurement data of manufactured MMICs is performed. The use of the integrated circuit of the switch is possible as a part of the switching nodes of the measuring microwave equipment.

Wideband 3-D-Printed Chip Interconnects for DC-Millimeter Wave Applications

Wide band and low-loss interconnects for millimeter wave applications are discussed in this work. The focus is to avoid using conventional techniques such as bond wires and solder bumps as they require matching networks, and are relatively narrow band. An Aerosol Jet 3-D printing technique is utilized to print the interconnects from the bare die chip to the package. These types of wideband, low-loss interconnects can contribute toward improving the overall RF front end performance. The proposed interconnects can operate over a wide frequency range of dc-50 GHz with reasonable insertion loss.

DC-10 GHz broadband linear power amplifier for 5G applications using 180 nm CMOS technology

This article suggests a broadband linear power amplifier (PA) for DC-10 GHz for Fifth-generation (5G) and multi-standard applications using 180 nm CMOS technology. The suggested radio frequency power amplifier is appropriate for wideband LTE, IoT, WSN, multi-standard, and 5G radio frequency transmitters. T-coil peaking and bridged-shunt-series peaking amplifiers are used for bandwidth extension and gain flatness. Also, the interstage matching inductors between common source and common gate transistors are applied to improve radio frequency achievement. The suggested PA consists of four stages as follows; input stage, two stages using the T-coil peaking technique, and the last stage utilizing bridged-shunt-series peaking topology. The input stage is a complementary current reuse (CCR) common gate with active shunt feedback (SFB) architecture. It is utilized to extend the matching of RF input impedance with agreeable linearity and power gain at little power consumption. The second stage works in class-C operation to enhance the efficiency and reduce DC power consumed whereas the class-AB mode is utilized in the third and fourth stages to improve the output power. The suggested PA obtains a peak constant power equal to 14.25 dBm, a maximum Power-Added-Efficiency (PAE) of 16 %, and a peak gain equal to 22 dB. The proposed power amplifier dissipates a DC power of 80 mW. The die size of the proposed power amplifier equals 1mm2, whereas the total chip size includes the pads is 1.62mm2.

A Wideband 6-Bit Digital Attenuator in a GaAs pHEMT MMIC

A low insertion loss, wideband 6-bit digital step attenuator is implemented in the 0.25-μm GaAs pHEMT process. Modified π- or T-type attenuator structures are adopted to expand the operation frequency bandwidth and reduce the insertion phase violation. Furthermore, the through-wafer via (TWV) is analyzed to reduce the influence of the parasitic effect on the high-frequency performance of the attenuator. The depletion mode single-gate switch transistors are used to control the on-off state of the attenuator, which provides low insertion loss and high isolation. The step of the attenuator is 0.5 dB, and the attenuation range is 31.5 dB. The measurement results show a maximum root mean square (RMS) attenuation error of 0.51 dB and RMS phase error of 6.6 degrees from DC-18 GHz. The chip area is 1.8 × 0.6 mm2.

A High Performance 0.18 μm RF Switch for Multi-Standard

This paper proposes a stacked field-effect transistor (FET) single-pole, double-throw (SPDT) RF switch which is capable of multi-standard. Negative voltage generator (NVG), logic controller, level shifter, and RF Switch branches are integrated. A PMOS self-biased strategy is proposed to improve linearity and simplify the design of the logic controller and level shifter. In order to reduce the influence of NVG, a new charge pump (CP) is proposed, and a low pass filter (LPF) is added to stabilize bias voltages. A new layout of the switch FET is proposed to minimize the product of on-state resistance and off-state capacitance (time constant). The RF switch proposed in this paper was implemented in the 0.18 μm silicon on insulator (SOI) process. The measured results show the P1 dB of 40 dBm, and the isolation (ISO) and insert loss (IL) at 1 GHz/5 GHz of 37 dB/22 dB, and 0.36 dB/0.55 dB. The operating frequency range is DC-6 GHz. Supply current is 37uA with the supply voltage of 2.6V.

Design and development of broadband DC-10 GHz packaged RF MEMS switches with on chip CPW-microstrip transitions

Design and development of broadband DC-10 GHz packaged RF MEMS switches with on chip CPW-microstrip transitions

High Linearity DC-38 GHz CMOS SPDT Switch

In this paper, we demonstrate a low-loss and high-linearity DC-38 GHz CMOS SPDT switch for 5G multi-band communications in 0.18 μm CMOS. Traveling-wave matching (CLCL network) is used for the output-port (ports 2 and 3) matching and isolation enhancement, while π-matching (CLC matching) is adopted for the input-port (port 1) matching. Positive/negative gate-bias is adopted for linearity enhancement because larger Pin (i.e., AC signal with larger negative Vin) is required to conduct the off-state series switch transistor. Negative-body bias is used for insertion-loss reduction because the off-state series switch transistor is closer to an open state. The SPDT switch achieves insertion loss of 0.4–1.4 dB, 3.6–4.3 dB, and 4.5–5.9 dB, respectively, for DC-6 GHz, 21–29 GHz, and 31–38 GHz. Moreover, the SPDT switch achieves isolation of 37.5–59.4 dB, 25.7–28.7 dB, and 24.3–25.2 dB, respectively, for DC-6 GHz, 21–29 GHz, and 31–38 GHz. At 28 GHz, the SPDT switch achieves remarkable input 1-dB compression point (IP1dB) of 25.6 dBm, close to the simulated one (28 dBm). To the authors’ knowledge, this is one of the best IP1dB results ever reported for millimeter-wave (mm-wave) SPDT switches.

25–53 GHz ultra‐wideband high‐isolation passive balanced duplexer on 0.18‐ μ m BiCMOS for 5G applications

A new ultra-wideband millimetre-wave passive balanced duplexer (DUX), employing a lumped-element Wilkinson power divider and grounded-centre-tap transformer, has been developed using 0.18-m BiCMOS process for fifth generation operations at 28, 37, 39 GHz, and beyond. The developed DUX is configured single-ended transmitter (TX) and antenna (ANT) ports and differential receiver (RX) port. It has an inherent matching at TX, RX and ANT ports, high TX–RX isolation, and highly balanced differential RX waveforms, and is ready for direct integration with a differential low-noise amplifier. Analysis has been performed to confirm the DUX's characteristics and assess its performance. Measured isolation from TX to each single-ended RX port is higher than 50 and 40 dB from dc-20 GHz and dc-60 GHz, respectively. Measured insertion loss from TX to antenna is better than 6.3 dB across 13–53 GHz. Measured insertion loss from ANT to differential RX port is lower than 13.8 dB from 25 to 57 GHz with 10.8 dB at 40 GHz. The core chip only occupies 0.3 mm2.

Design of a Wideband Surface Mountable Suspended Integrated Strip-Line Technology

This paper presents a low-loss surface mountable suspended integrated strip-line (SISL) technology. A DC-20 GHz thru transmission line and an eleventh-order generalized Chebyshev lowpass filter (LPF), with a cutoff frequency of 18 GHz, are simulated, fabricated, and measured to demonstrate the first-ever surface mountable suspended strip-line designs. Measured results of the thru line show less than 1 dB of insertion loss and greater than 10 dB of return loss across the 20 GHz bandwidth. Moreover, measured results of the LPF show less than 1 dB of insertion loss and greater than 10 dB return loss across the 18 GHz passband, as well as greater than 30 dB of suppression above 19 GHz. The proposed SMT SISL technology also has advantages of compact size, light-weight, low cost, and elimination of the extended circuit to be a multi-layer board following the trend to reduce the size, weight, power, and cost (SWaP-C).

A 30–40 GHz CMOS Receiver Front-End with 5.9 dB NF and 16.5 dB Conversion Gain for Broadband Spectrum Sensing Applications

A broadband receiver front-end with low noise figure and flat conversion gain response is presented in this paper. The receiver front-end is a part of the broadband spectrum sensing receiver and processes 30–40 GHz of broad input spectrum followed by down-conversion to DC-10 GHz of IF signal. The proposed work is comprised of a low noise amplifier (LNA), on-chip passive Balun, down conversion mixer, and output buffer. To achieve front-end target specification over 10 GHz input bandwidth, the stagger-tuned LNA is employed and the down conversion mixer is loaded with a 3rd-order LC ladder low pass filter. The prototype chip was implemented in 45 nm CMOS technology. The chip achieves 10.3–16.5 dB conversion gain, 5.9 dB integrated NF, and −11 dBm IIP3 from 30 to 40 GHz. The chip is realized within 0.42 mm 2 and consumes 96 mW from a 1.2 V supply.

Design and Analysis of a Low Loss, Wideband Digital Step Attenuator With Minimized Amplitude and Phase Variations

A compact, low loss, wideband digital step attenuator (DSA) is presented. The proposed DSA utilizes amplitude/phase-compensated T-type attenuator cells, in which the locations of poles and zeros are manipulated for minimizing variations in attenuation and phase. In addition, the reduced T-type attenuator cells that eliminate series switch transistors are used to achieve low insertion loss (IL). These techniques provide wideband (dc-20 GHz) operation for the DSA, with significantly decreased attenuation/phase errors and reduced IL. The DSA was implemented in a 130-nm silicon-germanium (SiGe) BiCMOS platform. The full attenuator circuit has binary-coded 6-bit digital control inputs with a least significant bit of 0.5-dB attenuation. It has a root-mean-square (rms) attenuation error of 0.37 dB and an rms phase error of 4°, both at 20 GHz. The IL and the input 1-dB compression point at 10 GHz are 4 dB and 10 dBm, respectively. The active core layout area is 0.14 mm2 (1.0 mm $\times $ 0.14 mm).

The Evolution of Channelization Receiver Architecture: Principles and Design Challenges

This paper presents a broadband receiver architecture with series and parallel channelization. The proposed architecture decomposes the broadband incident spectrum into multiple channels, and achieves fast switching time, while using the single synthesizer with a fixed local oscillator (LO) frequency. Channelized receiver is a good candidate for critical RF processing tasks, such as data conversion, broadband radio, and spectrum analysis. The key feature of the proposed channelized receiver is the decomposition of the broadband frequency spectrum through parallel band partition and series channel selection. Relevant design challenges of the channelization receiver are discussed. In addition, the radio impairments determining the key performance of the radio are analyzed. The prototype receiver front-end was designed and implemented in 45 nm CMOS technology to demonstrate the effectiveness of the proposed architecture. The receiver front-end prototype splits an input spectrum of dc-40 GHz into four sub-bands with 10 GHz IF bandwidth and dissipates the average power of 33 mA and 60 mA from RF and LO blocks, respectively, while achieving <5 dB NF and <−145 dBc/Hz phase noise.

High Power Ku-Band T/R and SP4T Switches in SOI CMOS

This paper presents silicon-on-insulation (SOI) CMOS T/R and SP4T switches with high-power handling capability. The CMOS transistors are stacked and their sources and drains are biased for the high-power handling capability. The TQ trench of 0.18-m SOI CMOS process is properly placed to improve the substrate isolation between transistors. For the T/R switch, the measured insertion loss of Tx and Rx modes are 1.1 and 1.7 dB, respectively, in Ku-band (12–18 GHz). The measured isolation between Tx and Rx ports is 24 dB in the same frequency band. To author’s knowledge, this T/R switch shows the highest input 1-dB compression point of 34 dBm in Ku-band CMOS switches. The SP4T switch operates in DC-18 GHz, and the measured insertion loss and isolation are 2.4 and 19.5 dB, respectively, with the return loss of 9.3 dB. This chip sizes are 0.11 mm for the T/R switch and 0.12 mm for the SP4T switch.

Integration of microwave termination based on TaN thin films on ferrite substrates

Integration of microwave discrete devices such as isolators and circulators is highly desired for radar and communication platforms and in particular as components used in transmit and receive (T/R) modules. In those applications, Tantalum nitride (TaN) films are widely used as a surface mounted termination to improve the reliability and performance. In the current work, TaN thin films were directly deposited on polycrystalline ferrite substrate (Ni 0.3 Zn 0.7 Fe 2 O 4 ) to be integrated with isolators or circulators. The deposition conditions were first optimized to obtain suitable sheet resistance and near zero temperature coefficients of resistance (TCR). Next a 50 Ω microwave termination was designed and fabricated using standard photolithography techniques. Broadband measurements show that the terminator has a low voltage standing wave ratio (VSWR) of less than 1.20 in the frequency range of DC-20 GHz. The measured resistance was between 48 and 54 Ω.

An Interrogation Technique of FBG Cascade Sensors Using Wavelength to Radio-Frequency Delay Mapping

A technique is proposed to interrogate a distributed photonic sensor composed of seven standard fiber Bragg gratings in cascade. A microwave-modulated optical signal is launched into an FBG cascade and subsequently undergoes dispersion in standard single-mode fiber, so that the different Bragg wavelengths are mapped into the radio-frequency (RF) delays that determine the peaks in the electrical impulse response of the optical link. Shifts in Bragg wavelengths have been determined from the shifts in the impulse response's peaks by recording the link's RF response in the range dc-20 GHz using a vector network analyzer (VNA), and then performing its inverse Fourier transform. A resolution of 14 pm is experimentally demonstrated after zero-padding the VNA traces.

Novel DC-40 GHz MEMS series-shunt switch for high isolation and high power applications

This paper presents the design, fabrication, and characterization of a lateral contact series-shunt ohmic RF microelectromechanical systems (MEMS) switch actuated by an electrothermal actuator. Since the proposed RF MEMS switch is actuated electrothermally, it can be operated at an extremely low operation voltage of 0.16V. In this switch, two series switches are cascaded by a quarter wavelength section of transmission line suspended over the trench of the substrate to form a series-shunt configuration according to the principle of impedance transforming. By using a single bidirectional thermal MEMS actuator to control the signal, the switch provides higher reliability when through high power microwave signal. The measured results show that an insertion loss of 1.2dB or better is achieved from DC-40GHz. The isolation is −50dB at 5GHz, −45dB at 20GHz and −60dB at 35GHz. What is more, this switch also exhibits high linearity, and high power handing for DC-40-GHz applications. In the switch OFF state, self-actuation does not happen up to the input power of 40dBm at 1GHz. In the switch ON state, no significant insertion loss variations or problems in the contacts, due to the RF power, can be observed below 31dBm input power.

Design and analysis of non-uniform shaped RF MEMS switch

In this paper, we present a novel non-uniform shaped cantilever based DC contact radio frequency microelectromechanical systems (RF MEMS) switch. This switch can be employed for various wireless mobile applications in frequency range of DC-10 GHz as it shows excellent RF characteristics with low actuation voltage. The design is optimized in the terms of electrostatic actuation mechanism, which included switch beam thickness, beam gap, spring shape and materials. Also, it's optimized shape and size of contact geometry and material ensures the high reliability, high isolation and very low insertion loss. The main features of this switch are simplicity of structure, reliability of contact, excellent RF characteristics, low actuation voltage and excellent figure of merit. We investigate the proposed design with Coventorware software for electromechanical and electromagnetic analysis and, get very promising results. The paper briefly outlines the design of RF MEMS switch and also focuses on the analysis of various switching parameters.