A DC–20-GHz Impedance Tuner Using Power-Enhanced Stacked-FET Switch in 45-nm SOI CMOS

Abstract

This letter presents the development of a dc–20 GHz impedance tuner in a 45-nm silicon-on-insulator complementary metal–oxide–semiconductor (CMOS) process. The proposed tuner consists of several short transmission line sections and tunable capacitors made up of small interdigital capacitors and switches. To increase the power handling capability, a switch topology using triple-stacked transistors and parallel capacitors is developed. The combination of the tuner architecture and the capacitor-switch arrangement enables the new tuner to have wideband operation, good tuning range, low loss, and high-power handling. The fabricated tuner can operate with RF power up to 27 dBm and provide a characteristic impedance tuning range from 56 to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$36~\Omega $ </tex-math></inline-formula> over dc–20-GHz bandwidth. In different operating states, the tuner demonstrates an insertion loss of 0.25–1.25 dB, an output 1-dB compression point (OP1dB) of better than 24 dBm, and an input third-order intercept point (IIP3) of better than 40 dBm.