dB Total Harmonic Distortion Research Articles

A PVT-Robust and 73.9 mHz High-Pass Corner Instrumentation Amplifier with an SCF-SCR-PR Hybrid Feedback Resistor

Analog front-end (AFE) circuits play an important role in the acquisition of physiological signals with low-level amplitudes (from tens of μV to tens of mV) and broadband low-frequency ranges (from sub-Hz to several hundred Hz). Possessing a high input impedance, an instrumentation amplifier (IA) accurately amplifies signals with low amplitude and low frequency, making it suitable for AFE circuits. This work demonstrates a capacitively coupled IA whose feedback resistance is realized by the proposed hybrid resistor, consisting of a switched-capacitor low-pass filter, a switched-capacitor resistor, and a continuous-time low-pass filter. The capacitively coupled IA achieves tera-ohm (TΩ) resistance and is insensitive to process, voltage, and temperature (PVT) variations. The simulation results show that the proposed IA illustrates a high-pass corner of 73.9 mHz, and the change of its high-pass corner with temperature is 0.05 mHz/°C. With the variation in the PVT corners, the difference between the maximum and minimum values of the high-pass corner of the proposed capacitively coupled IA is only 0.06 Hz. The design was implemented in a 130 nm standard CMOS process. The AFE with the proposed capacitively coupled IA achieves a 53.9 dB signal-to-noise and distortion ratio (SNDR) and 69.5 dB total harmonic distortion (THD).

A 17 GHz inductorless low‐pass filter based on a quasi‐Sallen–Key approach

SummaryIn this paper, an evolution of the Sallen–Key biquad architecture is presented, suitable for applications at very high frequency. The pole of the buffer amplifier is exploited as one of the poles of the biquad, therefore overcoming the constraints it poses on the maximum resonance frequency that can be achieved. This allows designing low‐pass filters with cutoff frequencies above 10 GHz without using bulky inductors and with good linearity performance provided by the use of feedback. This approach has been exploited to design a biquad in a commercial SiGe BiCMOS technology with maximum of about 320 GHz. The biquad has been designed to provide a resonance frequency of 12 GHz and a quality factor Q of 1.9; postlayout simulations show a cutoff frequency in excess of 17 GHz, 15.75 mW of power consumption, an equivalent input noise below 1 Vrms, and −52 dB of total harmonic distortion (THD) for a 640 mVpp input signal, with a very limited area consumption.

A 60GS/s Two-Stage Sampler with a Linearity Calibration Loop for PAM-8 Receivers

In this article, we show a 60 GS/s two-stage 8 × 8 time-interleaved sampling circuit, where the second-stage nonlinearity can be controlled by using the voltage that optimizes the static distortions of the sampler. A calibration algorithm can extract the nonlinear contributions of the stages and compensate for them by setting the optimal bias voltage. This can also be used to cancel the front-end nonlinear effects. The sampler was verified by implementing it in TSMC 5 nm FinFET, and a calibration system in a Pulse Amplitude Modulation transceiver, detecting and minimizing the nonlinearities, is presented. The optimum voltage biasing of the sampler was obtained by co-simulating the circuit with the linearity calibration loop implemented in Verilog-A. The histogram of the sampled signal at the slicer input is shown before and after the calibration to show the improvement in the sampled eye opening. Moreover, the resulting bias is equal to the one that maximizes the total harmonic distortion in transient simulations with a 1 GHz input signal, obtaining a minimum of 48.5 dB of total harmonic distortion across different PVT conditions.

A Low Distortion Audio Amplifier

The paper presents a design and assembly of a high-quality audio amplifier. The design is simple, and it can achieve extremely low Total Harmonic Distortion (THD) less than −100 dB for a bookshelf speaker with output power levels up to 10 W. The solution for a high-quality output are transistor pairs used in the input stage along with a simple topology that does not need matched transistor pairs for a power stage. Such input and output stages were closely analyzed at different bias currents. It was found out that there is an optimal power stage bias current of 20 mA for lowest distortion. The THD of the proposed topology was simulated with the LTSpice simulator and measured with the audio spectrum analyzer U8903B from Keysight and by a simple solution using a handheld recorder and an integrated Digital to Analog Converter (DAC). The Keysight was able to measure −104.5 dB THD R , whereas simple solution did measure −92.8 dB.

A 0.6 V 4 GS/s −56.4 dB THD Voltage-to-Time Converter in 28 nm CMOS

A 0.6 V low-voltage voltage-to-time converter (VTC) has been presented in this work for the emerging energy-efficient time-domain circuits and systems. The proposed VTC supports a rail-to-rail input by leveraging shrink sampling with two cascaded voltage sampling and charge sharing switches, breaking the tradeoff between linearity and input range of the traditional VTC and enabling low voltage operation. The charging current source is adjustable to calibrate the VTC gain variation. In addition, a 4-bit tunable delay buffer is inserted at the output stage to calibrate the VTC time offset, enhancing the PVT performance. By resizing the push-pull inverters’ PMOS/NMOS size ratio in the output buffer chain, the jitter contribution from buffers has been reduced. It also recovers the signal’s pulse width consumed during the voltage-time conversion, facilitating the time signal processing following VTC. Designed and fabricated in 28 nm CMOS, the prototype VTC occupies a 0.0012 mm² active area. Measurement results show that the VTC can run up to 4 GHz at a 0.6 V power supply, achieving -56.4 dB total harmonic distortion (THD) with Nyquist input and consuming 2.1 mW.

A Capacitively Coupled CT Δ ΣM With Chopping Artifacts Rejection for Sensor Readout ICs

This paper presents a sensor readout integrated circuit (ROIC) using a capacitively coupled instrumentation amplifier (CCIA)-embedded continuous-time ΔΣ modulator (CT ΔΣM) incorporating chopping artifact rejection. Chopping is an essential technique for suppressing the offset and 1/f noise. However, the chopping artifacts in the modulator loop degrade the in-band noise, linearity, and loop stability. In the proposed design, chopping aliasing is avoided by setting the chopping frequency ( f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ch</sub> ) same as the sampling frequency ( f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">s</sub> ). The chopping ripple is mitigated using the ripple reduction loop (RRL), and the shaped quantization noise-folding resulting from the RRL is prevented by minimizing the loop gain and bandwidth of the RRL. The residual ripple and spikes are filtered out using the alias rejection band of CT ΔΣM. The third-order loop filter enables sufficient noise-shaping with a low oversampling ratio (OSR). The chip is implemented in a 180-nm CMOS process with an active area of 1.65 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , drawing 232.2 μA at a 1.8 V supply. The proposed capacitively coupled (CC)-CT ΔΣM has a 19.4 nV/ √{Hz} input-referred noise density, 1.9 μV offset, 0.08% gain error, 16 ppm integral nonlinearity (INL), and 140 dB common-mode rejection ratio (CMRR) within an input range of 60 mV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">pp</sub> . With -110.1 dB total harmonic distortion (THD), excellent dynamic linearity performance is achieved owing to the CCIA-integrated design and chopping artifact rejection technique.

A Minimum-Voltage Driving Amplifier with Adaptive Three-Stage Open-Loop Gain and Folded Cascade Class-AB Output Current Control

A driving amplifier capable of operating at a minimum voltage is proposed, aiming to subdue the distortion effect caused by large amplitude driving at the hearing aid loudspeaker. Since the linearity of a cascode amplifier usually degrades with the reduced supply voltage, a three-stage cascade amplifier having a parallel cascade second stage, and a folded cascade Class-AB output current control in place are designed. With such an arrangement, the open loop gain should still be maintained at a sufficiently high level even in the presence of increased output amplitude. Also, the minimum supply voltage required can then be reduced to merely [Formula: see text]. Fabricated on a 0.18[Formula: see text][Formula: see text]m complementary metal oxide semiconductor (CMOS) process, the proposed amplifier achieves [Formula: see text][Formula: see text]dB total harmonic distortion [Formula: see text] with a loudspeaker load of 100[Formula: see text]ohm while operating from a 1.2[Formula: see text]V supply and being subject to a 1[Formula: see text]kHz sinusoidal input.

Single Phase Grid-tie Inverter Design Using PLL and MPPTTechniques

This paper focuses on designing and implementing a grid-tie inverter, which can convert DC voltage from the PV systems into an AC voltage using pulse width modulation technique. The proposed inverter is synchronized with the local grid to provide an alternate solution for the energy generation. To obtain the maximum power from the inverter maximum power point tracking technology is used. Using MPPT, approximately 95% power efficiency was achieved. Boost converter is designed to boost the voltage from solar panels to 240V. Phase locked loop circuit is utilized to synchronize the output frequency of the inverter with that of the local utility grid. Phase locked loop circuit uses phase detector to detect the phase difference between the reference (utility grid) frequency and the quiescent (required) frequency set in Voltage Controlled Oscillator. This quiescent frequency is converted to match with the reference frequency. This converted or synchronized frequency is then used as a reference for pulse width modulation controller to generate Pulse Width Modulation waveform. Using PLL, phase or frequency matching between utility grid’s electricity and inverter’s electricity was achieved in just 0.6 seconds. In the end, filtering system is designed using LMS filter and KALMAN filter to remove the noise from inverter output. A total of -22.63 dB total harmonic distortion was achieved using Kalman filter and were proved to be better than LMS filter. The simulation results provided in this report show the efficacy of the proposed grid-tie inverter.

A Multiphase Class-D Automotive Audio Amplifier With Integrated Low-Latency ADCs for Digitized Feedback After the Output Filter

A $5 \times 80$ W class-D audio power amplifier for automotive applications is presented. The amplifier is implemented in a 140-nm bipolar CMOS DMOS SOI. Configurable digital-loop filters can compensate for a range of LC output filters and their high loop gain (>50 dB between 20 Hz and 20 kHz) suppresses non-idealities of the output filter and enables low-cost output filter components. Key elements are the integrated low-latency $\Delta \Sigma$ analog to digital converters (ADCs) which digitize the output signals directly at the speaker load, after the output filter. The ADCs use filtering finite impulse response digital to analog converters in their feedback path to create an input–output transfer with a negative group delay at low frequencies. The ADCs have 116-dBA DR and −108 dB total harmonic distortion (THD). The bridge-tied load amplifier supports multiphase pulse-width modulation for lower electromagnetic interference. It operates with supplies from 6 to 25 V and with loads down to $1\Omega$ and achieves 19- $\mu \text{V}$ idle noise (Awtd) and 0.004% THD + N.

A 1V-70dB THD Digital Controlled Audio AGC

This paper presents a 1V -70dB THD audio Automatic Gain Control (AGC) circuits. The proposed AGC is based on feedback topologies and the gain is digital controlled. A π-type resistors network is used in the Programmable Gain Amplifier (PGA) as the passive feedback device to realize gain linearity in decibels and increase the gain accuracy. The hysteresis comparator eliminate the chattering effects when the output signal of Peak Detector changes rapidly around the threshold. The design is implemented in 0.18μm CMOS and occupies an active area of 0.41mm2. The power consumption of AGC is about 0.17mW at 1V supply voltage. The gain of PGA in the AGC loop ranges from 0dB to 40dB in 2dB step with gain error not more than 0.2dB. The integrated noise in the audio range (20 Hz~20 kHz) is 2.28μVRMS when the gain is set at 40dB. The total harmonic distortion (THD) is below -70dB over the audio frequencies at 0.4-Vpp differential output.

21.5 dBm‐IIP3 22.5 MHz fourth‐order follow‐the‐leader‐feedback analogue filter

A 4th-order single-loop follow-the-leader-feedback (FLFB) low-pass continuous-time filter in CMOS 0.18 µm is hereby presented. The outstanding FLFB noise behaviour is exploited to allocate the power consumption to linearity performance. The low-pass filter prototype features 22.5 MHz−3 dB frequency, 21.5 dBm-IIP3 and 76 µVRMS input referred in-band integrated noise. The overall power consumption is 7 mA from a 1.8 V supply voltage. The signal-to-noise ratio for a −40 dB-total harmonic distortion is 69 dB.

A 12.5 mW, 11.1 , −115 dB THD, Settling, 18 bit SAR ADC Driver in 0.6 CMOS

A driver amplifier suitable for integration with an 18 bit 500 kS/s successive approximation register analog-to-digital converter (ADC) is reported. It accepts single-ended or fully differential inputs. The driver consumes 12.5 mW from a 5 V supply, has a −115 dB (−120 dB) total harmonic distortion for 8 Vppd output at 1 kHz (10 kHz), a 240 ns settling time to 0.01% accuracy for a 2 Vppd output step, and an input-referred noise of 11.1 $\text{nV}/\sqrt{\text{Hz}}$ . Simulated 18 bit settling time is 900 ns, and $3\sigma$ input-referred offset is 1.2 mV. This is one of the first reported 18 bit CMOS ADC driver amplifiers, and its performance is comparable to that of the state-of-the-art parts in other processes.

Synergy Micro-Electronics Technology with a High Linearity BiCMOS Sample-and-Hold Circuit

A high accuracy BiCMOS sample and hold (S/H) circuit employed in the front end of a12bit 10 MS/s Pipeline ADC is presented. To reduce the nonlinearity error cause by the sampling switch, a signal dependent clock bootstrapping system is introduced. It is implemented using 0.6 um BiCMOS process. An 88.77 dB spurious-free dynamic range (SFDR), and a -105.20 dB total harmonic distortion (THD) are obtained.

Low-Distortion Sine Wave Generation Using a Novel Harmonic Cancellation Technique

A novel technique is proposed to generate robust, low distortion sine waves. In this method, outputs of a phase shift oscillator (PSO) are weighted and summed to obtain multiple outputs with very low distortion and precise phase relationship. The method allows a programmable number of harmonic distortion components to be cancelled over a wide frequency range. This work derives the condition for the weights on the outputs of the PSO to be a real quantity, and demonstrates how this can be used to generate low distortion sine waves. With the proposed method, in an N-stage PSO, harmonics up to N-2th can be canceled. Simulation results using commercial operational amplifier spice models are presented to demonstrate low distortion sine wave generation over 2 kHz-180 kHz frequency range. The method has been experimentally verified using extremely low-cost, discrete components to produce 100 dB total harmonic distortion (THD) sine wave.

Electronically tunable CMOS class-AB output stage

A new technique for CMOS class-AB output stages is introduced in this Letter. The technique uses a master---slave configuration of a complementary common-source output stage. It offers the advantage that the quiescent and minimum currents of the output stage can be independently tuned. The effectiveness of the proposed technique was verified by simulations using a standard n-well 0.18 μm CMOS process with 1 V supply voltage. A voltage buffer, that includes the proposed output stage, is able to drive a capacitive load of 0.5 nF obtaining ?63 dB total harmonic distortion. The topology features also power efficiency of about 63% for a pure resistive output load equal to 50 ?.

A 330 MHz 11 bit 26.4 mW CMOS Low-Hold-Pedestal Fully Differential Sample-and-Hold Circuit

A new technique for realizing a very-high-speed low-power low-voltage fully differential CMOS sample-and-hold circuit with low hold pedestal is presented. To achieve high sampling linearity the circuit utilizes linearized input switches. The fully differential design relaxes the trade-off between sampling speed and the sampling precision. The circuit design of major building blocks is described in detail. A prototype circuit in a 0.35-μm CMOS process is designed and experimental results are presented. The sample-and-hold circuit operates up to 330 MHz of sampling frequency with less than −68.3 dB of total harmonic distortion, corresponding to 11 bits for an input 80.24 MHz sinusoidal amplitude of 1.2V pp at a 3 V supply. This total harmonic distortion measurement reflects the held values as well as the tracking components of the output waveform. In these conditions, a differential hold pedestal of less than 0.8 mV, 0.8 ns acquisition time at 1.2 V step input, and 1.2V pp full-scale differential input range are achieved. The circuit dissipates 26.4 mW with a 3 V power supply.

A 20 GS/s 1.2 V 0.13 $\mu\hbox{m}$ CMOS Switched Cascode Track-and-Hold Amplifier

A low voltage, low power, high sampling rate track-and-hold amplifier (THA) architecture is proposed. The THA samples at 20 GS/s and combines a distributed amplifier and a switched cascode stage. Power consumption for the circuit is 71 mW and it occupies 0.09 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> in 0.13 μm CMOS. The THA delivers up to 34 dB spur-free dynamic range (SFDR) and -32 dB total harmonic distortion (THD) at a supply voltage of 1.2 V. Input return loss remains below -10 dB over all frequencies of interest, while output return loss remains below -15 dB.

An 8-bit 120-MS/s Interleaved CMOS Pipeline ADC Based on MOS Parametric Amplification

This brief presents an 8-bit 120-MS/s time-interleaved pipeline analog-to-digital converter (ADC) fully based on MOS discrete-time parametric amplification. The ADC, fabricated in a 130-nm CMOS logic process, features an active area below 0.12 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , where only MOS devices are used. Measurement results for a 20-MHz input signal shows that the ADC achieves 39.7 dB of signal-to-noise ratio, 49.3 dB of spurious-free dynamic range, -47.5 dB of total harmonic distortion, 39.1 dB of signal-to-noise-plus-distortion ratio, and 6.2 bits of peak effective number of bits while consuming less than 14 mW from a 1.2-V supply.

A 105 dB DR, -101 dB THD+N Sigma-Delta Audio D/A converter with A Noise-shaping Dynamic Element Matching Technique

A Sigma-Delta audio digital-to-analog (D/A) converter with a noise-shaping dynamic element matching (NSDEM) technique is presented . The proposed NSDEM technique has the advantage of less computation and also can be implemented with all-digital circuits easily. The converter is fabricated in a 0.35 μm CMOS process, occupies 2.85 mm2, and achieves 105 dB dynamic range -101 dB total harmonic distortion plus noise.

A Highly Linear Low-Voltage Source-Degeneration Transconductor Based on Unity-Gain Buffer

A complementary metal oxide semiconductor (CMOS) transconductor based on a high performance unity-gain buffer driving the degeneration resistor was used to obtain a highly linear voltage-to-current conversion with considerable reduction of the supply voltage. Simulations show that the transconductor using an 0.18-μm standard CMOS process with a 1.2-V supply voltage has less than −80 dB total harmonic distortion (THD) for a 1-MHz 0.4-V p-p differential input signal. The third-order intermodulation is less than −63 dB for 0.25 V p-p differential inputs at 1 MHz. The DC power consumption in the transconductor core is 240 μW. This topology is a feasible solution for low voltage and low power applications.