A 12.5 mW, 11.1 , −115 dB THD, Settling, 18 bit SAR ADC Driver in 0.6 CMOS

Abstract

A driver amplifier suitable for integration with an 18 bit 500 kS/s successive approximation register analog-to-digital converter (ADC) is reported. It accepts single-ended or fully differential inputs. The driver consumes 12.5 mW from a 5 V supply, has a −115 dB (−120 dB) total harmonic distortion for 8 Vppd output at 1 kHz (10 kHz), a 240 ns settling time to 0.01% accuracy for a 2 Vppd output step, and an input-referred noise of 11.1 $\text{nV}/\sqrt{\text{Hz}}$ . Simulated 18 bit settling time is 900 ns, and $3\sigma$ input-referred offset is 1.2 mV. This is one of the first reported 18 bit CMOS ADC driver amplifiers, and its performance is comparable to that of the state-of-the-art parts in other processes.