This paper characterizes a design analysis of low power (LP) and low voltage (LV) optimized low noise amplifier (LNA) for wide band applications. With review discussion on design challenges of LP and LV, a new biasing metric has been introduced for radio frequency analog circuit. The proposed LNA consists of two stages, the first stage is a current reuse topology, in which a combination of PMOS transistor stack on top of NMOS transistor has been used with series inductive peaking in the feed-back loop. It helps a lot to achieve the target of LP and LV, while the second stage is a mutually coupled CS stage, used for wideband matching to enhance the bandwidth and noise figure (NF). For optimization of passive component parameters of proposed LNA, particle swarm optimization (PSO) algorithm has been used. All the simulations have been done for a range of frequency 0–35 GHz in Cadence Virtuoso software 45-nm CMOS technology. The results quoted 18.57 dB maximum voltage gain, 2.4 dB NF, 17.1 dB S11, 16.6 dB S21, at frequency 25.4 GHz with 0.8 V, 1.6 mW broad band LNA.