dB Noise Figure Research Articles

A Miller N-Path Bandpass Filter with Improved Second Harmonic Rejection

While a Miller N-path filter is capable of channel selection at RF, it cannot sufficiently reject harmonic responses before going through the baseband circuitry. To suppress the second harmonic at the LNA output, this paper adds a feedback path to the conventional Miller N-path filter. The added feedback path distinguishes between the first and the second harmonic and exhibits a relatively large loop gain for the latter. As a result, the design suppresses the second harmonic at RF nodes. This is achieved without losing the desired characteristics of a conventional Miller N-path at the fundamental harmonic. The design example is a 500-MHz four-path filter simulated with the 90 nm CMOS. It achieves 13 dB gain, 2.6 dB noise figure, and $$+$$ 9.6 dBm out-of-band IIP3 at 50 MHz offset from the center frequency and burns 16 mW of power.

A 40-GHz Bandwidth Tapered Distributed LNA

In this brief, a design technique for tapered distributed low-noise amplifiers (LNAs) is presented. A circuit model is developed for gain and noise analysis of a nonuniform distributed amplifier (DA). It is shown that by optimal tapering of gate and drain transmission lines and transistors, the tapered distributed LNA can provide lower broadband average noise figure (NF) compared to a uniform DA. A proof-of-concept integrated circuit is implemented using a 0.1- $\mu \text{m}$ GaAs pHEMT process. The amplifier provides average gain of 15.2 dB and 3-dB bandwidth of 43.3 GHz. The average NF of 2.3 dB and minimum NF of 2.0 dB are achieved over 2–40 GHz. The chip consumes 55 mA current from a 2-V supply.

A Highly-Integrated Low-Noise MICS Band Receiver RF Front-End IC with AC-Coupled Current Mirror Amplifier

This work presents a low-noise, low-power receiver RF front-end integrated circuit (IC) for 402–405[Formula: see text]MHz medical implant communications service (MICS) band applications using 0.18-[Formula: see text]m CMOS process. The proposed front-end employs an AC-coupled current mirroring amplifier in between the low-noise current-reuse transconductor amplifier and a single-balanced IQ mixer for improved gain and noise performance in comparison to previous works. The designed front-end IC achieves a simulated performance of 36.5[Formula: see text]dB conversion gain, 1.85[Formula: see text]dB noise figure, and IIP3 of [Formula: see text][Formula: see text]dBm while consuming 440[Formula: see text][Formula: see text]W from 1-V voltage supply. The consumed core layout area, including I/Q LO generation and current bias circuits, is only 0.29[Formula: see text]mm2.

Design of Low Noise Amplifier for 1.5 GHz

Low Noise Amplifier (LNA) is a front-end device of a radio frequency (RF) receiver used to increase the amplitude of an RF signal without much additional noise, thereby increasing the noise figure of the system. This paper presents design, simulation, and prototype of an LNA operating at 1.5 GHz for the bandwidth of 100 MHz. The circuit was simulated using Advanced Design System (ADS). The components used are Surface Mount Devices (SMDs); with transistor "Infineon BFP420" as a major component. Other components are resistors, capacitors, and inductors; inductors being superseded by microstrip lines. The circuit was fabricated on FR4 board. The measurements of several parameters of LNA were made using Vector Network Analyzer (VNA), Noise Figure Meter; and Spectrum Analyzer. The LNA has minimum gain of 15.4 dB and maximum noise figure of 1.33 dB. It is unconditionally stable from 50 MHz to 10 GHz. DC supply is 5V and the current consumption is 10 mA. This LNA offers Output-Third­Order-Intercept-Point (OJP3) of about 1 4 dBm.

A Comparative Study and Radial Performance Evaluation for Reflective EDFA Configurations with Optimized Intrinsic Parameter Sets

For the improvement of Gain and Reduction in Noise Figure, a range of Erbium Doped Fiber Amplifier (EDFA) based configurations from simple Single Pass (SP) EDFA to Quadruple Pass with Filter (QPF) EDFA have been investigated. Modified Giles model for rate and propagation equations has been proposed and subsequently used for Gain and Noise Figure evaluation for all configurations. The influence of EDFA based configurations on its internal design parameters is investigated to obtain an optimum design parameter set. Among the single stage EDFA configurations, Reflective Double pass with Filter (DPF) with a high optimum Numerical Aperture gives good radial performance with high signal overlap factor of 0.563 and Pump overlap factor of 0.834. For the dual stage configurations, second stage of Reflective QPF EDFA gives best signal overlap of 0.6727 and pump overlap of 0.8827, whereas it has the lowest pump threshold of 0.47 mW, hence highest pumping efficiency. At 1550 nm of input signal wavelength, maximum gain of 27.66 dB and low Noise figure of 5.4 dB was obtained in QPF EDFA at lowest pump power of 20 mW. Thus QPF EDFA is suitable choice for preamplifier applications at 1550 nm.

Phase-Modulated Analog Photonic Link With a High-Power High-Linearity Photodiode

We investigate phase-modulated analog photonic link performance using interferometric detection with a Mach–Zehnder interferometer (MZI) under different bias conditions and a high-power high-linearity modified unitraveling carrier (MUTC) photodiode (PD). Expressions for radio frequency (RF) small signal gain and the optimal MZI bias point for RF gain are derived, and noise figure (NF) and third-order spurious free dynamic range (SFDR3 ) are analyzed. Using a 28- μ m-diameter MUTC single PD with 23 dBm RF output power under 155-mA saturation current at 10 GHz, we measured a record-high link gain of 25 dB, 18 dB NF, and ${\text{114}}\;{\text{dB}} \cdot {\rm{H}}{{\rm{z}}^{{\text{2/3}}}}$ SFDR3 at 130 mA photocurrent with an optimally biased MZI. By using a 24- μ m-diameter balanced MUTC PD pair with 21 dBm RF output power at 108 mA at 10 GHz, we obtained a 16 dB link gain, 16 dB NF, and ${\text{118}}\;{\text{dB}} \cdot {\rm{H}}{{\rm{z}}^{{\text{2/3}}}}$ DR3 at 100 mA total dc photocurrent when the MZI was biased at quadrature. The RF gain at both MZI bias points is in good agreement with our calculations.

High performance photonic microwave frequency down-conversion using a dual-drive dual-parallel Mach-Zehnder modulator

ABSTRACTPhotonic microwave frequency down-conversion based on carrier suppression single sideband (CS-SSB) modulation via an integrated dual-drive dual-parallel Mach-Zehnder modulator (DP-MZM) is proposed. The MZM on the up path of the DP-MZM is used to generate SSB modulation signal, while the MZM on the bottom path of the DP-MZM is unmodulated. By adjusting the amplitude and phase of the unmodulated optical carrier, two optical carriers are cancelled out, which improves the performance of the system with reduced local oscillator (LO) power and large suppression of mixing spurious sidebands. The frequency down-conversion approach is theoretically analyzed and verified by simulation. Simulation results show that the power of frequency down-conversion signal is at least 39 dB higher than that of the mixing spurious sidebands. Besides, 9.5 dB gain, 2.8 dB noise figure (NF) and 1.9 dB spurious-free dynamic range (SFDR) improvements can be obtained compared with the previous OCS modulation frequency down-conversion scheme while the required LO power is 10 dB, 5 dB and 5 dB lower than that of the OCS modulation scheme, respectively.

Design of LNA for WAVE Application with Different Substrate

This work deals with the design of low noise amplifiers for WAVE (WLAN for vehicular environment) application which operates in 5.85–5.925 GHz frequency band considering the center frequency as 5.9 GHz. There are various substrates available in the market that can be used for designing LNA’s and some of them are considered in this work. Out of all the substrates used, RT Duroid 5880 provides better results with a power gain of 16.423 dB and optimum noise figure of 0.687 dB.

A fully integrated 4 × 2 element CMOS RF phased array receiver for 5G

This paper presents a fully integrated phased array receiver containing two four element radio frequency (RF) beamforming receivers supporting two multiple-input multiple-output channels. The receivers are designed and fabricated using 45 nm CMOS SOI technology. A 10 bit IQ vector modulator phase shifter (IQVM) is implemented in RF signal paths to control the phase and amplitude of the received signal before combining. Each IQVM provides 360° phase shift control and 17 dB gain variation. An off-chip, simultaneous high-Q impedance matching and bandpass filtering technique for each low-noise amplifiers is presented using non-uniform transmission line segments. Measured downconversion gain at 100 MHz intermediate frequency and noise figure (NF) of a single path are 23 and 5.4 dB, respectively, giving estimated 3.4 dB NF for a single element when simulated PCB and matching losses are taken into account. 1 dB compression point and Input third-order intercept point (IIP3) are − 37 and − 28 dBm, respectively. Each four-element receiver consumes 486 mW DC power from 1.2 V power supply. Total area of two receivers is 5.69 mm2.

Design of a constant-bandwidth variable-gain amplifier for LTE receivers

In this study, a constant-bandwidth variable-gain amplifier (VGA) is presented for long-term evolution (LTE) receivers. The presented VGA’s description is given with a newly proposed exponential-current generator, and also the common-mode feedback and the DC-offset cancellation (DCOC) circuits. The proposed exponential current generator is based on the Taylor series approximation in such a way that it can be expanded to meet the required gain control range. The simulations are performed using the TSMC 180 nm process technology with Cadence Analog Virtuoso. The VGA has a 45 dB gain control range, 180 MHz bandwidth, 15.7 dB m the third-order input-intercept point for minimum gain and below 20 dB noise figure for maximum gain which makes it convenient for LTE receivers. The simulations also show that the bandwidth of the VGA is fairly constant over the control range. Monte Carlo simulations reveal that by using a DCOC circuit, the VGA provides 30 dB output offset rejection. The overall power consumption of the circuit is 9.1 mW under a 1.8 V power supply.

Low‐power switched transconductance mixer and LNA design for Wi‐Fi and WiMAX applications in 65 nm CMOS

This study proposes a wide-band low-power low-noise amplifier (LNA) and switched transconductance (SwGm) mixer. The proposed mixer is realised with a fully differential complementary metal oxide semiconductor (CMOS) SwGm configuration. It provides a high bandwidth with a low noise figure (NF) and consumes a low amount of power. Moreover, an ultra-wideband LNA is designed by using a split-load inductive technique. The combination of the LNA and the mixer has provided competitive results in terms of power, bandwidth, NF, and gain. The LNA + mixer was designed and fabricated in the 65 nm radio frequency-CMOS technology. The proposed LNA achieves 2.5 ± 0.1 dB of NF and 17 ± 1.5 dB of gain over the band of 1-10 GHz and consumes 4.8 mW of power. The proposed SwGm mixer shows a maximum conversion gain (CG) of 10 dB, a minimum NF of 10 dB, and more than -8.5 dBm of third-order input intercept point (IIP3) over the band of 10 GHz. The implemented LNA + mixer achieves 19 dB of CG, 5 dB of NF, and -6 dBm of IIP3. The on-chip LNA and mixer consume only 1.65 mW and 530 μW, respectively, from a 1.2 V supply voltage.

Analysis and Design of Commutation-Based Circulator-Receivers for Integrated Full-Duplex Wireless

Previously, we presented a non-magnetic, nonreciprocal N-path-filter-based circulator-receiver (circ.-RX) architecture for full-duplex (FD) wireless which merges a commutation-based linear periodically-time-varying (LPTV) non-magnetic circulator with a down-converting mixer and directly provides the baseband (BB) receiver signals at its output, while suppressing the noise contribution of one set of the commutating switches. The architecture also incorporates an on-chip balance network to enhance the transmitter (TX)-receiver (RX) isolation. In this paper, we present a detailed analysis of the architecture, including a noise analysis and an analysis of the effect of the balance network. The analyses are verified by simulation and measurement results of a 65 nm CMOS 750 MHz circulator-receiver prototype. The circulator-receiver can handle up to +8 dBm of TX power, with 8 dB noise figure (NF) and 40 dB average isolation over 20 MHz RF bandwidth (BW). In conjunction with digital self-interference (SI) and its third-order intermodulation (IM3) cancellation, the FD circ.-RX demonstrates 80 dB overall SI suppression for up to +8 dBm TX average output power. The claims are also verified through an FD demonstration where a -50 dBm weak desired received signal is recovered while transmitting a 0 dBm average-power OFDM-like TX signal.

A 1V 1.4 mW multi-band ZigBee receiver with 64 dB SFDR

A low voltage low power receiver supporting 780/868/915/2400 MHz ZigBee bands is presented in this paper. The receiver exploiting low-IF architecture consists of a RF-to-BB (baseband) current reuse front-end, a Gm-C based variable gain complex band-pass filter (CBPF) for image rejection and four stages of limiting amplifiers which saturate IF signal for demodulation. The proposed ZigBee receiver chip is implemented in TSMC 180 nm CMOS technology with metal-insulator-metal (MIM) capacitors. PCB measurement results show that the receiver has 45.9 dB conversion gain, 8.5 dB NF and −33.5 dBm out-of-band IIP3 at sub-GHz bands. When working in 2.4 GHz band, the gain is 38.4 dB, noise figure (NF) is 16.7 dB and the out-of-band IIP3 is −28.2 dBm. The S11 bandwidth (S11 < −10 dB) can cover the entire ZigBee spectrum (700–2500 MHz). The receiver consumes 1.42 mW from a 1 V DC supply and the die size is 1.41 mm2 including all pads.

A wide-band noise-cancelling direct-conversion balun-LNA-mixer front-end

A wide-band noise-cancelling balun-LNA-mixer front-end for direct conversion receivers is presented in this paper. The proposed circuit exploits an on-chip noise cancelling balun-LNA to achieve low noise figure. This paper presents a novel technique to reduce the noise of the auxiliary amplifier which, in the conventional noise cancelling circuits, is designed to cancel out the noise of the main amplifier. The proposed front-end is designed and simulated in TSMC 0.18 µm RF technology. Simulation results with Spectre, show the high conversion gain of 25.7–28.9 dB and low noise figure of 3.3–3.9 dB all-over the frequency band of 2–4.5 GHz. Also, the S11 of the proposed front-end stays below − 9.3 dB entire the band of interest. IIP2 and IIP3 of the proposed front-end are achieved 67.8 dBm and − 17.4 dBm, respectively. The proposed circuit consumes 17.8 mW power from 1.8 V voltage supply.

An Ultra-Low Power 28 nm FD-SOI Low Noise Amplifier Based on Channel Aware Receiver System Analysis

This study investigates the benefit of an optimal and energy-efficient reconfiguration technique for the design of channel-aware receiver aiming Internet of Things (IoT) applications. First, it demonstrates the interest for adaptive receivers based on an estimation of the received power and compares the proposed channel-aware receiver with the State Of the Art. It is shown that the lifetime of the Wireless Sensor (WS) battery can be extended by a factor of five with the optimization of operating points of the tunable receiver while maintaining similar performances than industrial modules. The design of an Ultra-Low Power (ULP) inductorless Low Noise Amplifier (LNA), which fits the low power mode of the tunable receiver, is then optimized and described. The back-gate biasing of Fully Depleted Silicon-On-Insulator (FD-SOI) technology to lower the power consumption by more than 25% still maintaining performances is evaluated. The proposed LNA has been implemented in ST-Microelectronics 28 nm FD-SOI Technology, its active area is only 0.0015 mm2. The measured performances at 2.4 GHz exhibit more than 16 dB of voltage Gain (Gv), 7.3 dB of Noise Figure (NF), and a −16 dBm Input referred third-order Intercept Point (IIP3). The LNA consumes 300 µW from a 0.6 V supply.

A 28 GHz LNA using defected ground structure for 5G application

AbstractIn this article, a defected ground structure (DGS) is proposed to replace the inductor placed between common source and common gate stage in cascode low‐noise amplifier (LNA), leading to silicon area reducing as well as good internal matching condition. For verification, a 28 GHz three‐stage cascode LNA with DGS is designed and implemented in a 130‐nm CMOS technology. The fabricated prototype achieves a peak gain of 20 dB and minimum noise figure of 5.2 dB. The LNA occupies small silicon area of only 0.12 mm2 excluding testing pads, and it draws a current of 16 mA from a 1.5 V supply voltage.

Gallium arsenide 0.5–18 GHz antenna front‐end with integrated limiter and differential to single ended low‐noise amplifier

In this study, the authors present a 36:1 relative bandwidth active front-end low-noise amplifier (LNA) with power limiter that has been developed for airborne ultra-wideband receiver systems. The proposed system is driven by an external antenna with a balanced mode with an input impedance of 150 Ω. The whole microwave monolithic integrated circuit (MMIC) embeds a protection from the presence of high-level signals, an ultra-wideband amplifier circuit, an active balun and an impedance transformer. It has a bandwidth ranging from 0.5 to 18.0 GHz with 14 dB gain, 4.5 dB noise figure (NF), 20 dB common-mode rejection and 30 dBm input overload protection. The circuit has a single bias from the output port greatly simplifying its use within a receiving system and can be directly integrated into the antenna mechanical support. Test measurements are also provided.

Design of Self-Differential Down-Conversion I/Q Mixer for 2.4 GHz IoT Application

A 2.4 GHz self-differential down-conversion Gilbert cell mixer with current-reuse topology is presented in this paper. This design is targeted for low-power IoT applications. Here, by using a novel self-differential RF input stage with current-reuse topology, the single-ended RF signal can be transferred into differential signals without using a balun. With an applied local oscillator (LO) power of 10 dBm and RF signal of -30 dBm, this mixer demonstrates 9.886 dB of conversion gain, 10.4 dB of noise figure at 5 MHz and an IIP3 of 1.1767dBm in both I/Q branch. The design consumes 1.57 mA from a 1.8 V voltage supply.

Noise in phase-(in)sensitive dual-core fiber parametric amplification.

Flat and wide-bandwidth gain spectrum, along with phase-sensitive gain with no need to generate amplifier input idlers, can be achieved with a coupled dual-core fiber optical parametric amplifier. In this paper, we analyze the noise properties of such an amplifier. We achieve a 3 dB noise figure in the phase-insensitive case and a minimum of -6 dB noise figure in the phase-sensitive configuration. An alternative phase-sensitive configuration is also studied, that avoids the use of idlers at the input of the amplifier, leading to a 3 dB flat spectrum combined noise figure for the output signals. Pump transfer noise in phase-insensitive and phase-sensitive configurations is also studied along with the noise figure variation against the length of the amplifier.

A Wideband Variable Gain LNA With High OIP3 for 5G Using 40-nm Bulk CMOS

This letter presents a CMOS wideband variable gain LNA for 28-GHz 5G integrated phased-array transceivers preserving high third-order intercept point (OIP3) at all gain settings. The prototype LNA has three stages providing digitally controlled gain optimized for higher IIP3 at lower gain. The stages are coupled together using double-tuned transformers for maximum group delay flatness. Fabricated in a 40-nm CMOS process, it achieves 18–26 dB gain at 1-dB gain step with 12–14.5 dBm OIP3 and 3.3–4.3 dB noise figure, while consuming 21.5–31.4 mW across 26–33 GHz frequency range. The root-mean-square error of the gain steps is less than 0.38 dB.