Abstract
In this brief, a design technique for tapered distributed low-noise amplifiers (LNAs) is presented. A circuit model is developed for gain and noise analysis of a nonuniform distributed amplifier (DA). It is shown that by optimal tapering of gate and drain transmission lines and transistors, the tapered distributed LNA can provide lower broadband average noise figure (NF) compared to a uniform DA. A proof-of-concept integrated circuit is implemented using a 0.1- $\mu \text{m}$ GaAs pHEMT process. The amplifier provides average gain of 15.2 dB and 3-dB bandwidth of 43.3 GHz. The average NF of 2.3 dB and minimum NF of 2.0 dB are achieved over 2–40 GHz. The chip consumes 55 mA current from a 2-V supply.
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