Current Reuse Topology Research Articles

Design and Analysis of a Wideband K/Ka-Band CMOS LNA Using Coupled-TL Feedback

We demonstrate a low power (PD) 22-33 GHz CMOS low-noise amplifier (LNA) with low noise-figure (NF) and small group-delay (GD) variation for 28 GHz 5G system. Body-selfforward-bias (BSFB) technique, i.e., connection of transistor’s body to drain via body resistance, is used for threshold and supply voltage reduction, and substrate leakage suppression. Gain and NF enhancement at the same PD is achieved because lower VDD and higher transconductance (due to larger bias current) are used. Current-reused topology is used for low PD. Coupled transmission -line (TL) feedback neutralization technique is proposed for further gain and NF enhancement. The feedback from output (drain) to input (gate) via gate-drain capacitance (Cgd) can be cancelled by the feedback from drain (through source) to gate via the coupled TL and gate-source capacitance (Cgs). The LNA consumes 12.2 mW and achieves S21 of 16 dB, 3 dB bandwidth (f3dB) of 11 GHz (22-33 GHz), minimum NF (NFmin) of 2.5 dB, average NF (NFavg) of 3.1 dB, and GD variation of ±6 ps for 22-33 GHz, and figure-of-merit (FOM) of 91.7 GHz. Moreover, the LNA achieves input third-order intercept point (IIP3) of -3 dBm. The NF and FOM are one of the best results ever reported for LNAs with f3dB greater than 7 GHz and PD lower than 15 mW.

An X-Band State Adjustable Low Noise Amplifier Using Current Reuse Technique

This article presents an on-chip state-adjustable 8 GHz~12 GHz low-noise amplifier (LNA). It has two characteristics. First, an improved current reuse topology is proposed. By connecting a small capacitor in parallel with the drain of the first-stage transistor, the bandwidth is expanded and the in-band flatness is improved. Second, an innovative adaptive bias circuit is designed to cope with the influence of temperature and process on the performance of the amplifier, and a design method for on-chip adjustment of the chip state is proposed for the first time. As a result of these technologies, the chip area is 1.1 mm × 0.8 mm, the chip provides 24.4 dB nominal gain with merely 0.75 dB noise at 10 GHz, and yields 14.5 dBm output power at 1 dB compression point (OP1dB) when biased at 30 mA quiescent current, meanwhile, gain, OP1dB, and quiescent current can be adjusted on-chip. This design improves the comprehensive performance of X-band LNA and provides more flexibility for system engineers in application. The chip is fabricated using Win Semiconductors’ 0.15 um InGaAs pHEMT E-mode process.

A Low Power ROIC with Extended Counting ADC Based on Circuit Noise Analysis for Sensor Arrays in IoT System

As the Internet of Things (IoT) is rapidly integrated into our daily life, the demand for high performance readout integrated circuit (ROIC) design for sensor arrays is boosting. This paper presents a low power, low noise ROIC with 14-bit column-parallel extended counting (EC) ADCs for sensor arrays targeting the IoT applications. The proposed EC-ADC adopts a pseudodifferential architecture to cancel even-order nonlinearity. The analog front-end is a G m stage, which employs a current-reuse topology to boost the transconductance and reduce noise without increasing current consumption. The upper 9-bit conversion is implemented during integration, and the residual voltage is converted by a 5-bit single-slope (SS) ADC, where the comparator is reused. A ping-pong integrator is proposed to reduce the reset time and improve linearity, eliminating the power-hungry CTIA structure. The ROIC is designed in 0.18 μm 1P5M CMOS process for a 640 × 480 sensor array. Power consumption of the ROIC is 33 mW, and each column ADC consumes 40.1 μW. Simulation results show an input-referred noise of 0.89 LSB (1.74 μVrms), an integral nonlinearity of +0.92/-0.70 LSB, an ENOB of 12.87 bits, and a FoM of 131.1 fJ/step.

A 3-GHz Inverse-Coupled Current-Reuse VCO Implemented by 1:1 Transformer

A voltage-controlled oscillator (VCO) based on a current-reuse (CR) topology is proposed. By inversely coupling two CR VCOs through tank inductors, the proposed VCO inherits the good phase noise performance of CR VCO, and meanwhile can realize differential outputs and alleviate the disturbance of VCO to the power supply and ground. Also, the proposed VCO achieves a phase noise improvement due to the electro-magnetic coupling of a transformer. Fabricated in the 180-nm CMOS process, the core circuit of the proposed VCO occupies an area of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.4\times0.32$ </tex-math></inline-formula> mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . Under a supply voltage of 1.2 V, the measured tuning range is 2.88–3.61 GHz (22.5%). The phase noise at 1-MHz offset varies between −126.7 and −123 dBc/Hz among the tuning range. The figure of merit (FoM) is in the range of 188.1–190.7 dBc, at 1-MHz offset.

Small Group Delay Variation and High Efficiency 3.1–10.6 GHz CMOS Power Amplifier for UWB Systems

A two-stage cascaded power amplifier (PA) employing a proposed Resistor-Capacitor (RC) interstage was provided and simulated. The current-reuse topology is employed at the first stage to lower the power consumption, while the RC interstage helps to enrich the gain flatness and the wideband matching. The shunt peaking topology in a common source configuration is adopted at the second stage to enhance the power gain. The postlayout simulation is performed using the TSMC 65 nm CMOS process operating in a frequency band of 3.1 GHz to 10.6 GHz. The postlayout simulation results indicate that a high flat gain of approximately 22.8 ± 1.2 dB, small group delay variation of ±50 ps, and good input and output matching of less than −10 dB are achieved over the desired working band. Moreover, a saturated output power of 10 dBm and maximum power-added efficiency (PAE) of 29.5% is achieved at 6 GHz. The proposed PA consumes the low power of 15.5 mW from 1.2 V supply voltage.

A 2.4 GHz 87 μW low-noise amplifier in 65 nm CMOS for IoT applications

As the Bluetooth devices for the internet of things require extremely low-power dissipation to maintain longer battery life, a low-noise amplifier (LNA) as the main power-consuming part in the circuit needs more current-efficient topologies on power saving. This paper proposes a low-noise transconductance amplifier that combines the techniques of passive impendence transformation, [Formula: see text]-boosting technique, and current reuse, leading to a low power under the 1.2 V power supply. The transformer-based [Formula: see text]-boosted structure is applied in the four-transistor-stacked current-reuse topology leading to a [Formula: see text] power saving. The proposed LNA simulated in 65 nm CMOS shows the NF of 3.3 dB and the IIP3 of −8 dBm, respectively, while dissipating 87 [Formula: see text]W dc power. Compared to the previous low-power LNA, this design has fairly low-power consumption and low NF while other performance metrics remain competitive.

An Ultra-Low-Power K-Band 22.2 GHz-to-26.9 GHz Current-Reuse VCO Using Dynamic Back-Gate-Biasing Technique

An ultra-low-power K-band LC-VCO (voltage-controlled oscillator) with a wide tuning range is proposed in this paper. Based on the current-reuse topology, a dynamic back-gate-biasing technique is utilized to reduce power consumption and increase tuning range. With this technique, small dimension cross-coupled pairs are allowed, reducing parasitic capacitors and power consumption. Implemented in SMIC 55 nm 1P7M CMOS process, the proposed VCO achieves a frequency tuning range of 19.1% from 22.2 GHz to 26.9 GHz, consuming only 1.9 mW–2.1 mW from 1.2 V supply and occupying a core area of 0.043 mm2. The phase noise ranges from −107.1 dBC/HZ to −101.9 dBc/Hz at 1 MHz offset over the whole tuning range, while the total harmonic distortion (THD) and output power achieve −40.6 dB and −2.9 dBm, respectively.

Realization of LNA and Mixer Using CMOS 0.18μm Technology for 3.1 to 10.6 GHz

In this paper, low noise amplifier and mixer circuits are realized using 0.18μm CMOS technology in the frequency range of 3.1 to 10.6 GHz. LNA circuit uses the cascade topology with source degeneration technique, which help in reducing the non-linearity in the circuit. The current reuse topology is used to decrease the biasing voltage and hence to decrease the power consumption in the circuit. Realized circuit simulated in 0.18μm technology and various results shows highest gain S21 is 19.982dB and has the positive value in the entire frequency band, minimum NFmin is 1.270dB occurs at 1.27GHz and the highest NFmin is 3.4dB. S11 i.e. input reflection coefficient is -31.670dB and it is negative throughout the entire frequency range while the reflection at output port is report to be -7.449 dB. The resistive feedback topology helps in getting the flat gain in the frequency. Mixer circuit is also realize in 0.18μm CMOS technology, which uses current bleeding topology. Transformer help in converting the single ended signal into differential format. Maximum value of gain is 6.584dB, gain is positive in the entire RF frequency range, S11 i.e. the reflection at port1, which give the negative values in the entire frequency band, simulation of S12 i.e. leakage between the port 1 and 2 has negative values in the entire frequency band means proper isolation between the ports. The future work can the realization of the superheterodyne receiver in UWB band.

A Novel Low Noise Instrumentation Amplifier for Bio-Medical applications

In this work we propose an efficient and a novel Instrumentation amplifier design fabricated using CMOS technology that can be used for the amplification of bio-medical signals. Instrumentation Biological amplifiers play a crucial role in biomedical devices like hearing aids, pacemaker etc. An instrumentation amplifier with current feedback and Current re-use topology along with the Chopper Offset-stabilization technique which was used in op-amps will also be extended to current-feedback instrumentation amplifiers, will help us to minimize and eliminate the flicker (1/f) noise and the offset voltages that will occur during the design of the feedback amplifiers. The gain mismatch problems that usually occurs due to the use of Current re -use topology was also minimized by the use of dynamic element matching technique that will be described in the paper. The design is simulated using Cadence Spectre tool. The Instrumentation amplifier final layout is designed in Cadence Layout editor with 0.18um CMOS technology.

Analysis and Design of a Broadband Output Stage With Current-Reuse and a Low Insertion-Loss Bypass Mode for CMOS RF Front-End LNAs

This article presents a comprehensive analysis of a novel broadband output stage for external RF front-end low-noise amplifiers (eLNAs). Both variants of the output stage are manufactured using a 130nm bulk CMOS technology. They utilize a common-drain output stage with current-reuse topology, switchable resistive feedback, and source-degeneration. Also, a novel inductor-less low insertion-loss bypass mode is implemented for enhanced bypass functionality. The LNAs are implemented with 4 gain modes achieving excellent RF performance in all possible mobile communication scenarios. Furthermore, an auxiliary linearization circuitry (NMOS IMD sinker) is implemented for variant β to improve linearity performance in low gain mode. Besides, the LNAs support all frequency bands between 1.4GHz and 2.7GHz by only changing the external matching component, allowing easy adaption to different frequency bands. Two offered solutions are realized with a die size of only 0.16mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and 0.11mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , respectively. The power consumption is 6.0mW in high gain, 3.6mW in low gain and active-bypass and 0.12mW in bypass mode using a supply voltage of 1.2V. Moreover, a 5.15GHz LNA with high-Q on-chip matching and the broadband output stage is realized and manufactured using a 60nm RF SOI technology. A NF performance of only 1.15dB is achieved consuming only 6.0mW power.

60 GHz Common-Gate Single-Stage Current Reuse Cascode LNA Topology for High-Data-Rate Applications

In the design of complementary metal oxide semiconductor (CMOS) radio-frequency (RF) components, power dissipation and speed are the two important and conflicting factors which lay stringent requirements on RF design. In this work, a low-noise amplifier (LNA) is designed by using common-gate (CG–CG) current reuse topology and a cascode amplifier with current mirror feedback. The CG–CG low-noise amplifier with current reuse topology attains maximum forward gain of 11 dB and minimum noise figure of 3.2 dB at the desired 60 GHz using 90-nm CMOS virtuoso cadence technique. The designed LNA gives both input and output matching $$< -10$$ dB at 60 GHz and a power dissipation of 7.5 mW.

Enhanced Digital Synthesized Phase Locked Loop with High Frequency Compensation and Clock Generation

The proposed work concentrates on the integration of an 8-GHz voltage-controlled oscillator (VCO) and a frequency tripler for 24-GHz local oscillator generation. By stacking the VCO and the tripler with a current-reused topology, the power consumption of this integration can be saved. The proposed circuit with a total chip area of 0.7 mm ×0.8 mm is implemented in a 0.18 μm CMOS process. As the tuning voltage increases from 0 to 2 V, the measured frequency tuning range (FTR) of the VCO is from 7.06 to 8.33 GHz. The final resulting output frequency from the tripler ranges from 21.18 to 24.98 GHz (16.5% FTR). The core circuit totally consumes 5 mA from a 1.8-V supply voltage. The measured phase noises at the VCO and frequency tripler outputs are − 113.76 and − 105.1 dBc/Hz at 1-MHz offset frequency, respectively, when Vtune is 0 V. The best evaluated figure of merit with tuning is − 187.2 dBc/Hz (decibels relative to carrier). Closed form equations allow for a performance driven design for both PLL and estimator. By using a variable sample frequency controlled by the PLL, the Kalman filter is always operated around its center frequency, which is the rated grid frequency. The new topology is compared to other published single-phase PLL designs and its operation is verified by both simulations and experiments. This integration of a VCO and a frequency tripler exhibits a high potential for the use in low-power 24-GHz phase-locked loops. The PLL designed using dual mode logic technique exhibits excellent performance even under severely distorted utility grid voltage conditions. This robustness makes it very suitable for use in systems connected to grids having an important share of non-linear loads.

Multi-Mode 60-GHz Radar Transmitter SoC in 45-nm SOI CMOS

This article introduces an architecture for a millimeter-wave multi-mode radar transmitter IC, which supports three key radar waveforms: 1) continuous-wave (CW/FMCW); 2) pulse; and 3) phase-modulated continuous-wave (PMCW), all from a single front end. The proposed IC, implemented in a 45-nm CMOS silicon-on-insulator (SOI) process for operation in the 60-GHz band, integrates a broadband frequency tripler, a two-stage pre-amplifier, two power mixers, and mixed-signal baseband waveform generation circuitry. The transmitter radar operation in multiple modes is enabled by configuring the power mixers and the associated waveform baseband circuitry. An important advantage of this approach is that the overall signal bandwidth, a key performance metric in radar, is limited only by the RF output nodes in pulse generation. A novel broadband frequency tripler design technique based on a current-reuse topology is also proposed for LO generation with >59% output fractional bandwidth. On-wafer measurement results for the full TX IC in CW mode show an average output power of 12.8 dBm from 54 to 67 GHz with a peak power of 14.7 dBm and the harmonic rejection ratio >27 dB. The measurement in pulse mode demonstrates programmable pulsewidth from 20 to 140 ps, which translates to >40-GHz radar signal bandwidth. The PMCW mode operation is also demonstrated in this case with 10-Gb/s PRBS modulated radar signal. The IC consumes 0.51 W and occupies $2.3\times 0.85$ mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> of die area excluding pads.

A Low-Noise Amplifier Utilizing Current-Reuse Technique and Active Shunt Feedback for MedRadio Band Applications

In this work, a low-power 0.18-μm CMOS low-noise amplifier (LNA) for MedRadio applications has been designed and verified. Cadence IC5 software with Silterra’s C18G CMOS Process Design Kit were used for all design and simulation work. This LNA utilizes complementary common-source current-reuse topology and subthreshold biasing to achieve low-power operation with simultaneous high gain and low noise figure. An active shunt feedback circuit is used as input matching network to provide a suitable input return loss. For test and measurement purpose, an output buffer was designed and integrated with this LNA. Inductorless design approach of this LNA, together with the use of MOSCAPs as capacitors, help to minimize the die size. On post-layout simulations with LNA die area of 0.06 mm2 and simulated total DC power consumption of 0.5 mW, all targeted specifications are met. The simulated gain, input return loss and noise figure of this LNA are 16.3 dB, 10.1 dB and 4.9 dB respectively throughout the MedRadio frequency range. For linearity, the simulated input-referred P1dB of this LNA is -26.7 dBm while its simulated IIP3 is -18.6 dBm. Overall, the post-layout simulated performance of this proposed LNA is fairly comparable to some current state-of-the-art LNAs for MedRadio applications. The small die area of this proposed LNA is a significant improvement in comparison to those of the previously reported MedRadio LNAs.

A 3.5-GHz Class-F Power Amplifier with Current-Reused Topology in 0.13-μm CMOS for 5G Application

In this paper, a 3.5-GHz class-F Power Amplifier with current-reused topology in 0.13-[Formula: see text]m CMOS for 5G application is presented. This proposed circuit has a two-stage structure by a current-reused topology driving to improve gain and the stability of PA. An output matching network is constructed by an open-circuited third harmonic resonator that can integrate the current and voltage waveform in the time domain adopted to improve the output power and reduce power consumption. The simulation results show that the proposed PA provides a 13[Formula: see text]dBm output power with a PAE of 50.5% and a small signal gain of 32.5[Formula: see text]dB that is higher than reported for a two-stage design in CMOS at the 3.5-GHz frequency, while the minimum output return loss ([Formula: see text]) is [Formula: see text]14.4[Formula: see text]dB with a minimum value of [Formula: see text]24.67[Formula: see text]dB. Many experiments are carried out to prove that the proposed PA has higher gain and higher efficiency compared to the traditional class-F power amplifier and is suitable for 5G short-range applications. Finally, the layout occupies a compact chip area of [Formula: see text][Formula: see text]mm2, including testing pads.

Performance analysis of low power LNA using particle swarm optimization for wide band application

This paper characterizes a design analysis of low power (LP) and low voltage (LV) optimized low noise amplifier (LNA) for wide band applications. With review discussion on design challenges of LP and LV, a new biasing metric has been introduced for radio frequency analog circuit. The proposed LNA consists of two stages, the first stage is a current reuse topology, in which a combination of PMOS transistor stack on top of NMOS transistor has been used with series inductive peaking in the feed-back loop. It helps a lot to achieve the target of LP and LV, while the second stage is a mutually coupled CS stage, used for wideband matching to enhance the bandwidth and noise figure (NF). For optimization of passive component parameters of proposed LNA, particle swarm optimization (PSO) algorithm has been used. All the simulations have been done for a range of frequency 0–35 GHz in Cadence Virtuoso software 45-nm CMOS technology. The results quoted 18.57 dB maximum voltage gain, 2.4 dB NF, 17.1 dB S11, 16.6 dB S21, at frequency 25.4 GHz with 0.8 V, 1.6 mW broad band LNA.

An ultra-low power amplifier for wearable and implantable electronic devices

This paper presents an ultra-low-power CMOS amplifier for Low-frequency biosignal recording applications, especially for implantable biosensors and wearable or portable devices such as wearable electrocardiogram (ECG) recording microsystems that power consumption and on-chip area are the critical constraints. The proposed amplifier consists of two stages. In the first stage, a current reuse topology is used to achieve a lower input-referred voltage noise power density compared to a normal single-ended common source amplifier. In order to reduce the on-chip area, an inverter based amplifier with high output impedance is used at the output stage of the circuit to reduce the area occupied by the large load capacitance, which is required for having low cut off frequency of 200 Hz. Using this technique, the required load capacitance is decreased to about 2.1 pF. To reduce the power consumption, a ± 0.6 V supply voltage is used, and the transistors are pushed toward sub-threshold region to reduce the bias currents to about 260 nA in the first and the second stages. To validate the design, the proposed amplifier is simulated using 0.18 μm TSMC CMOS technology with Cadence in post-layout level. It is shown that the total power consumption of the proposed amplifier is as low as 640 nW. The proposed amplifier benefits from a CMRR >125 dB, total input-referred noise of 6.1 μVrms in 200 Hz bandwidth for ECG signal recording, and a closed-loop gain of about 35.1 dB. The layout of the circuit occupies a total area of 0.034 mm2.

A 790 nW Low-Noise Instrumentation Amplifier for Bio-Sensing Based On Gm-RSC Structure

This paper presents a low-power low-noise instrumentation amplifier (IA) for bio-potential recording. The proposed IA is based on a novel Gm-RSC structure, whose gain is determined by the transconductance (Gm) and the equivalent resistance ([Formula: see text]) of the switched-capacitor (SC) load. The transconductance amplifier stage is based on the current-reuse telescope topology to achieve low noise at low-power dissipation. A resistor-controlled oscillator is designed to generate desirable operational frequency for SC load and to continuously tune the mid-band gain of the IA for different biomedical applications. Measurement results show that the input referred noise of the proposed IA is about 1.27[Formula: see text][Formula: see text]VRMS ([Formula: see text][Formula: see text]Hz) and the noise efficiency factor is 3.3. The range of tunable gain is from 28 to 40[Formula: see text]dB. The common mode rejection ratio and power supply rejection ratio at 50[Formula: see text]Hz are 72 and 78[Formula: see text]dB, respectively. The IA consumes only 660[Formula: see text]nA current at 1.2[Formula: see text]V supply and the active area of the IA is only 0.035[Formula: see text]mm2.

Pre‐low noise amplifier (LNA) filtering linearisation method for low‐power ultra‐wideband complementary metal oxide semiconductor LNA

This study describes the use of a pre-low noise amplifier (LNA) third-order notch filter as a novel linearity enhancement technique for ultra-wideband complementary metal oxide semiconductor LNA current-reuse topology. The second/third order input intercept point (IIP2/3) has improved along the entire working bandwidth (BW) from 2.1 to 12.5 GHz. The suggested linearisation technique achieves maximum/minimum IIP2 improvement from 19.068 to 104.143 dBm at 6.4 GHz and from 22.5 to 57.42 dBm at 5.5 GHz, respectively. In addition, this work achieves maximum/minimum IIP3 improvement from −7.956 to 34.688 dBm at 6.4 GHz and from −9.986 to 8.281 dBm, respectively. Moreover, the suggested linearisation technique does not affect the total ultra-wideband (UWB)-LNA power consumption, which is only 6.7 mW. Furthermore, the linearised UWB-LNA average noise figure is 1.6535 dB at the entire working BW. The simulation is performed and optimised with an advanced design system utilising BSIM3v3 TSMC 180 nm model files at different temperature values.

A low power and high gain current-reused LNA using cascaded L-type input matching network

A wideband 2–3 GHz three-stage low noise amplifier (LNA) featuring current reuse, cascaded L-type input matching network (IMN), and optimized multiple gated transistors method (MGTR) using 0.18-μm CMOS technology is presented in this paper. The current-reused topology is employed in the first two stages to reduce power consumption. For a wideband input matching, the common gate (CG) topology is adopted. Moreover, the cascaded L-type IMN composed of two single L-type networks cascaded in series is proposed for the first time. To improve the linearity performance, the optimized MGTR taking both transconductance gm and third-order nonlinear coefficient gm″ into consideration is proposed and applied to the output stage. The proposed LNA presents a maximum power gain of 28.0 dB, an input matching across 1.8–5.8 GHz and a high third-order input intercept point (IIP3) of −9.89 dBm. A noise figure (NF) of 3.1–3.5 dB is obtained in the required band with a power dissipation of 6.49 mA from a 3 V power supply.