Critical Path Length Research Articles

Area-energy optimized ternary multiplier usingefficient design approaches in GNRFET technology

The semiconductor industry has long benefited from CMOS transistors in realizing advanced VLSI circuits. However, achieving area-energy optimization in CMOS-based VLSI circuits has become increasingly challenging due to short-channel effects. Another obstacle in manufacturing these transistors is the adoption of body-biasing techniques to adjust the threshold voltage (Vth) for developing ternary logic-based circuits. Researchers are now exploring emerging devices like graphene nanoribbon field-effect transistors (GNRFET) as potential candidates for future electronics. GNRFET devices not only leverage graphene’s remarkable properties but also benefit from the ability to achieve distinct Vth through tuning the width of graphene nanoribbons. This paper focuses on using tri-state 32-nm GNRFET devices to implement a novel area-energy optimized ternary multiplier circuit. To attain a logic ‘1′ in the proposed circuit, a power-efficient voltage division technique is employed. Additionally, efficient design approaches are used to reduce the critical path length and decrease the number of necessary transistors. Simulation results using HSPICE demonstrate that the proposed design reduces energy consumption by a minimum of 6.75% and up to 37.50% compared to other state-of-the-art 32-nm GNRFET-based TMUL circuits. Furthermore, the proposed design decreases both the area and complexity by utilizing a single-VDD and incorporating 24 transistors.

Hardware-Conscious Optimization of the Quantum Toffoli Gate

While quantum computing holds great potential in combinatorial optimization, electronic structure calculation, and number theory, the current era of quantum computing is limited by noisy hardware. Many quantum compilation approaches can mitigate the effects of imperfect hardware by optimizing quantum circuits for objectives such as critical path length. Few approaches consider quantum circuits in terms of the set of vendor-calibrated operations (i.e., native gates) available on target hardware. This manuscript expands the analytical and numerical approaches for optimizing quantum circuits at this abstraction level. We present a procedure for combining the strengths of analytical native gate-level optimization with numerical optimization. Although we focus on optimizing Toffoli gates on the IBMQ native gate set, the methods presented are generalizable to any gate and superconducting qubit architecture. Our optimized Toffoli gate implementation demonstrates an 18% reduction in infidelity compared with the canonical implementation as benchmarked on IBM Jakarta with quantum process tomography. Assuming the inclusion of multi-qubit cross-resonance (MCR) gates in the IBMQ native gate set, we produce Toffoli implementations with only six multi-qubit gates, a 25% reduction from the canonical eight multi-qubit implementations for linearly connected qubits.

Efficiency of Priority Queue Architectures in FPGA

This paper presents a novel SRAM-based architecture of a data structure that represents a set of multiple priority queues that can be implemented in FPGA or ASIC. The proposed architecture is based on shift registers, systolic arrays and SRAM memories. Such architecture, called MultiQueue, is optimized for minimum chip area costs, which leads to lower energy consumption too. The MultiQueue architecture has constant time complexity, constant critical path length and constant latency. Therefore, it is highly predictable and very suitable for real-time systems too. The proposed architecture was verified using a simplified version of UVM and applying millions of instructions with randomly generated input values. Achieved FPGA synthesis results are presented and discussed. These results show significant savings in FPGA Look-Up Tables consumption in comparison to existing solutions. More than 63% of Look-Up Tables can be saved using the MultiQueue architecture instead of the existing priority queues.

Improving Learning-Based DAG Scheduling by Inserting Deliberate Idle Slots

The increasing demands of computing capabilities make it expensive to operate a large-scale cloud cluster. A good scheduling algorithm should be able to reduce the average job completion time (JCT), which is the time duration between a job's arrival and its termination. However, when considering the precedence constraint of stages in each job, and when jobs arrive online, designing a scheduler to minimize the average JCT is challenging. Counterintuitively, we find that inserting idle time before some jobs might reduce the JCT, which is ignored by many schedulers. The state-of-the-art scheduler, which uses reinforcement learning (RL) techniques to solve scheduling problems, does not consider deliberate idle time. We integrate our observations to the RL agent and let the agent learn the best length of idle time. We carefully design the features used in RL. The shape of each job DAG is captured by the critical path length and the average width, and the detailed precedence constraints in each job DAG are extracted by graph neural networks. The experiment results on both synthetic and realworld datasets show that inserting the deliberate idle time could reduce the average JCT. Also, the results illustrate the significant contribution made by our proposed features.

Scheduling computations with provably low synchronization overheads

We present a Work Stealing scheduling algorithm that provably avoids most synchronization overheads by keeping processors’ deques entirely private by default and only exposing work when requested by thieves. This is the first paper that obtains bounds on the synchronization overheads that are (essentially) independent of the total amount of work, thus corresponding to a great improvement, in both algorithm design and theory, over state-of-the-art Work Stealing algorithms. Consider any computation with work \(T_{1}\) and critical-path length \(T_{\infty }\) executed by P processors using our scheduler. Our analysis shows that the expected execution time is \(O\left( \frac{T_{1}}{P} + T_{\infty }\right) \), and the expected synchronization overheads incurred during the execution are at most \(O\left( \left( C_{\mathrm{CAS}} + C_{\mathrm{MFence}}\right) PT_{\infty }\right) \), where \(C_{\mathrm{CAS}}\) and \(C_{\mathrm{MFence}}\), respectively, denote the maximum cost of executing a Compare-And-Swap instruction and a Memory Fence instruction.

Brain network analyses of diffusion tensor imaging for brain aging.

The approach of graph-based diffusion tensor imaging (DTI) networks has been used to explore the complicated structural connectivity of brain aging. In this study, the changes of DTI networks of brain aging were quantitatively and qualitatively investigated by comparing the characteristics of brain network. A cohort of 60 volunteers was enrolled and equally divided into young adults (YA) and older adults (OA) groups. The network characteristics of critical nodes, path length (Lp), clustering coefficient (Cp), global efficiency (Eglobal), local efficiency (Elocal), strength (Sp), and small world attribute (σ) were employed to evaluate the DTI networks at the levels of whole brain, bilateral hemispheres and critical brain regions. The correlations between each network characteristic and age were predicted, respectively. Our findings suggested that the DTI networks produced significant changes in network configurations at the critical nodes and node edges for the YA and OA groups. The analysis of whole brains network revealed that Lp, Cp increased (p < 0.05, positive correlation), Eglobal, Elocal, Sp decreased (p < 0.05, negative correlation), and σ unchanged (p ≥ 0.05, non-correlation) between the YA and OA groups. The analyses of bilateral hemispheres and brain regions showed similar results as that of the whole-brain analysis. Therefore the proposed scheme of DTI networks could be used to evaluate the WM changes of brain aging, and the network characteristics of critical nodes exhibited valuable indications for WM degeneration.

Innovative Dual-Binary-Field Architecture for Point Multiplication of Elliptic Curve Cryptography

High-performance Elliptic Curve Cryptography (ECC) implementation in encryption authentication severs has become a challenge due to the explosive growth of e-commerce’s demand for speed and security. Point multiplication (PM) is the most common and complex operation in ECC which directly determines the performance of the whole system. This article proposes a 6CC-6CC (clock cycle) dual-field PM architecture and a 6CC-4CC dual-field PM architecture based on maximizing utilization of Karatsuba multipliers and re-ordering schedule strategy in PM. The Montgomery Ladder algorithm used in PM is modified to a 4CC algorithm for better resource utilization and parallel computation. To solve the frequency drop problem while working on large finite field, the PM architectures for high and low field are carefully studied to have universal critical path length and balanced performance. Both of the architectures are implemented over GF(2571) and GF(2283) on Xilinx Virtex-5 and Virtex-7 FPGAs (Field-Programmable Gate Array) for comparison. The 6CC-6CC architecture is shown to have the best performance on GF(2571), which achieves one PM operation in $17.44~\mu s$ using 81549 LUTs (Look-Up-Table) with the frequency of 197.2 MHz on Virtex-5, and $12.55~\mu s$ using 80970 LUTs with the frequency of 274.1 MHz on Virtex-7. The 6CC-4CC architecture performs better on GF(2283) with the shortest computation time. It takes only $3.21~\mu s$ to finish one PM operation on Virtex-5 and $2.22~\mu s$ on Virtex-7, which are faster than all the previous designs. The implementation results prove that the proposed architectures have state-of-the-art performance as well as higher versatility for ECC designs.

Accelerating Deep Convolutional Neural Network base on stochastic computing

Deep Convolutional Neural Networks (DCNNs) are highly computational, and low budget platforms face many restrictions due to their implementation. Recently, Stochastic Computing (SC) demonstrated satisfying solution with simple and low power arithmetic units. In this paper, we present a highly efficient SC-based inference framework of DCNNs. We first propose a new Approximate Parallel Counter (APC), which is the most computational part in SC-DCNN. Our design relies on multiplexers to reduce the total number of input data. Second, a new mechanism is proposed for SC-based Rectified Linear Unit (ReLU) to make it more accurate and more similar to the actual ReLU function. Eventually, a new way is proposed for implementing soft-max function in SC domain with utilizing minimum resources. The simulation result shows that our platform for implementing LeNeT-5 achieves better area overhead, critical path length and power consumption than state-of-the-art works by term of slightly sacrificing accuracy.

HRHS: A High-Performance Real-Time Hardware Scheduler

This article represents an on-line time-predictable distributed hardware scheduler solution, suitable for many-core systems. We have partitioned the Main scheduler into uniform Partial schedulers to achieve a significant gain in term of performance and scalability, while software scheduling solutions impose excessive delays (in order of thousands of clock cycles) to a system. Although we have considered the implementation of the Earliest Deadline First (EDF) algorithm for each Partial scheduler, one can use customized scheduling policies, as needed. Designers can also modify different parts of our proposed architecture to obtain more suitable hardware for their design. HRHS outperforms conventional schedulers, in terms of resource utilization (LUT, register), delay and energy consumption by 36.83, 22.93, 46.36 and 59.26 percent on average, respectively. It also overpowers clustering solutions by circumventing their intrinsic off-line characteristics. The presented designs are also implemented in ASIC with 45-nanometer technology, in which the HRHS design excels in power, area and critical path length by 49.33, 50.67, and 53.33 percent on average, respectively, over other designs implemented in this article.

Fuzzy project scheduling with critical path including risk and resource constraints using linear programming

Project scheduling is one of the important issues of project management which has raised the interest of the researches, and several methods have been developed for solving this problem. While certain models are used in most studies, uncertainty is one of the intrinsic properties of most projects in real world which consist some activities with uncertain processing times and resource usages. In this paper, a fuzzy linear programming model is proposed for project scheduling considering risk and resources constraints under uncertain environment in which activity duration and the amount of resources used by each activity is defined as a fuzzy membership function. The proposed model is simulated in MATLAB R2009a software and four test cases adopted from the literature are implemented. The computational results show that the proposed model decreases the critical path length about 4% in competition with similar methods.

Fuzzy project scheduling with critical path including risk and resource constraints using linear programming

Project scheduling is one of the important issues of project management which has raised the interest of the researches, and several methods have been developed for solving this problem. While certain models are used in most studies, uncertainty is one of the intrinsic properties of most projects in real world which consist some activities with uncertain processing times and resource usages. In this paper, a fuzzy linear programming model is proposed for project scheduling considering risk and resources constraints under uncertain environment in which activity duration and the amount of resources used by each activity is defined as a fuzzy membership function. The proposed model is simulated in MATLAB R2009a software and four test cases adopted from the literature are implemented. The computational results show that the proposed model decreases the critical path length about 4% in competition with similar methods.

Feedforward-Cutset-Free Pipelined Multiply–Accumulate Unit for the Machine Learning Accelerator

Multiply–accumulate (MAC) computations account for a large part of machine learning accelerator operations. The pipelined structure is usually adopted to improve the performance by reducing the length of critical paths. An increase in the number of flip-flops due to pipelining, however, generally results in significant area and power increase. A large number of flip-flops are often required to meet the feedforward-cutset rule. Based on the observation that this rule can be relaxed in machine learning applications, we propose a pipelining method that eliminates some of the flip-flops selectively. The simulation results show that the proposed MAC unit achieved a 20% energy saving and a 20% area reduction compared with the conventional pipelined MAC.

Improving Performance under Process and Voltage Variations in Near-Threshold Computing Using 3D ICs

Near-threshold computing (NTC) circuits have been shown to offer significant energy efficiency and power benefits but with a huge performance penalty. This performance loss exacerbates if process and voltage variations are considered. In this article, we demonstrate that three-dimensional (3D) IC technology can overcome this limitation. We present a detailed case study with a 28nm commercial-grade core at 0.6V operation optimized with various 3D IC physical design methods. First, our study under the deterministic case shows that 3D IC NTC design outperforms 2D IC NTC by 29.5% in terms of performance at comparable energy. This is significantly higher than the 12.8% performance benefit of 3D IC at nominal voltage supplies due to higher delay sensitivity to input slew at lower voltages. Second, it is well demonstrated that transistor delay is more sensitive to voltage changes at NTC operation. However, our full-chip study reveals that IR drop effect on 2D/3D IC NTC performance is not severe due to the low power consumption and hence lower IR drop values. Third, die-to-die variation impact on full-chip performance is visible in 3D IC NTC designs, but it is not worse compared to 2D IC NTC designs. This is mainly due to the shorter critical path length in 3D IC NTC designs.

Resource Oblivious Sorting on Multicores

We present a deterministic sorting algorithm, Sample, Partition, and Merge Sort (SPMS), that interleaves the partitioning of a sample sort with merging. Sequentially, it sorts n elements in O ( n log n ) time cache-obliviously with an optimal number of cache misses. The parallel complexity (or critical path length) of the algorithm is O (log n log log n ), which improves on previous bounds for deterministic sample sort. The algorithm also has low false sharing costs. When scheduled by a work-stealing scheduler in a multicore computing environment with a global shared memory and p cores, each having a cache of size M organized in blocks of size B , the costs of the additional cache misses and false sharing misses due to this parallel execution are bounded by the cost of O ( S · M / B ) and O ( S · B ) cache misses, respectively, where S is the number of steals performed during the execution. Finally, SPMS is resource oblivious in that the dependence on machine parameters appear only in the analysis of its performance and not within the algorithm itself.

Optimization of the Critical Diameter and Average Path Length of Social Networks

Optimizing average path length (APL) by adding shortcut edges has been widely discussed in connection with social networks, but the relationship between network diameter and APL is generally ignored in the dynamic optimization of APL. In this paper, we analyze this relationship and transform the problem of optimizing APL into the problem of decreasing diameter to 2. We propose a mathematic model based on a memetic algorithm. Experimental results show that our algorithm can efficiently solve this problem as well as optimize APL.

Correlation-Aware Heuristics for Evaluating the Distribution of the Longest Path Length of a DAG with Random Weights

Coping with uncertainties when scheduling task graphs on parallel machines requires to perform non-trivial evaluations. When considering that each computation and communication duration is a random variable, evaluating the distribution of the critical path length of such graphs involves computing maximums and sums of possibly dependent random variables. The discrete version of this evaluation problem is known to be #P-hard. Here, we propose two heuristics, CorLCA and Cordyn, to compute such lengths. They approximate the input random variables and the intermediate ones as normal random variables, and they precisely take into account correlations with two distinct mechanisms: through lowest common ancestor queries for CorLCA and with a dynamic programming approach for Cordyn. Moreover, we empirically compare some classical methods from the literature and confront them to our solutions. Simulations on a large set of cases indicate that CorLCA and Cordyn constitute each a new relevant trade-off in terms of rapidity and precision.

A Counter example to the Forward Recursion in Fuzzy Critical Path Analysis Under Discrete Fuzzy Sets Full Text

Fuzzy logic is an alternate approach for quantifying uncertainty relating to activity duration. The fuzzy version of the backward recursion has been shown to produce results that incorrectly amplify the level of uncertainty. However, the fuzzy version of the forward recursion has been widely proposed as an approach for determining the fuzzy set of critical path lengths. In this paper, the direct application of the extension principle leads to a proposition that must be satisfied in fuzzy critical path analysis. Using a counterexample it is demonstrated that the fuzzy forward recursion when discrete fuzzy sets are used to represent activity durations produces results that are not consistent with the theory presented. The problem is shown to be the application of the fuzzy maximum. Several methods presented in the literature are described and shown to provide results that are consistent with the extension principle.

A 3D universal structure based on molecular-QCA and CNT technologies

This paper presents a novel method for design and implementation of three dimensional (3D) two-layer devices with 1/0 logic values. This method uses carbon nanotube (CNT) technology as well as the molecular quantum cellular automata (MQCA) technology on a graphene substrate. The most significant characteristic of the proposed design, which makes the design unique, is the capability of generating functions in 3D; the proposed method would allow implementation of the designs in a single layer which significantly impacts on reducing the chip area and also greatly facilitates the overall synthesis of the design including placement, routing and reducing the critical path length.

On-the-Fly Pipeline Parallelism

Pipeline parallelism organizes a parallel program as a linear sequence of stages. Each stage processes elements of a data stream, passing each processed data element to the next stage, and then taking on a new element before the subsequent stages have necessarily completed their processing. Pipeline parallelism is used especially in streaming applications that perform video, audio, and digital signal processing. Three out of 13 benchmarks in PARSEC, a popular software benchmark suite designed for shared-memory multiprocessors, can be expressed as pipeline parallelism. Whereas most concurrency platforms that support pipeline parallelism use a “construct-and-run” approach, this article investigates “on-the-fly” pipeline parallelism, where the structure of the pipeline emerges as the program executes rather than being specified a priori . On-the-fly pipeline parallelism allows the number of stages to vary from iteration to iteration and dependencies to be data dependent. We propose simple linguistics for specifying on-the-fly pipeline parallelism and describe a provably efficient scheduling algorithm, the P iper algorithm, which integrates pipeline parallelism into a work-stealing scheduler, allowing pipeline and fork-join parallelism to be arbitrarily nested. The P iper algorithm automatically throttles the parallelism, precluding “runaway” pipelines. Given a pipeline computation with T 1 work and T ∞ span (critical-path length), P iper executes the computation on P processors in T P ≤ T 1 / P + O ( T ∞+lg P ) expected time. P iper also limits stack space, ensuring that it does not grow unboundedly with running time. We have incorporated on-the-fly pipeline parallelism into a Cilk-based work-stealing runtime system. Our prototype Cilk-P implementation exploits optimizations such as “lazy enabling” and “dependency folding.” We have ported the three PARSEC benchmarks that exhibit pipeline parallelism to run on Cilk-P. One of these, x264 , cannot readily be executed by systems that support only construct-and-run pipeline parallelism. Benchmark results indicate that Cilk-P has low serial overhead and good scalability. On x264 , for example, Cilk-P exhibits a speedup of 13.87 over its respective serial counterpart when running on 16 processors.

Work-Efficient Matrix Inversion in Polylogarithmic Time

We present an algorithm for inversion of symmetric positive definite matrices that combines the practical requirement of an optimal number of arithmetic operations and the theoretical goal of a polylogarithmic critical path length. The algorithm reduces inversion to matrix multiplication. It uses Strassen’s recursion scheme, but on the critical path it breaks the recursion early, switching to an asymptotically inefficient yet fast use of Newton’s method. We also show that the algorithm is numerically stable. Overall, we get a candidate for a massively parallel algorithm that scales to exascale systems even on relatively small inputs.