Critical Path Length Research Articles

Error-correction coding in CMOS RAM resistant to the effect of single nuclear particles

Coders/decoders that are used in RAM to enhance the data storage reliability on exposure to single nuclear particles are analyzed. If the numbers of check bits are equal, a Hsiao decoder has a lower signal propagation delay than a decoder of the modified Hamming code. A decoder of the extended Hsiao code with additional check bits has the lowest delay among all decoders. When Hsiao decoders with units with a truncated correction circuit, a symmetrically simplified circuit for error vector calculation, and a circuit forming the error signal without the use of the error vector are used in RAM, the critical path lengths and the occupied chip area may be reduced if the detection of triple errors is excluded. The equal efficiency of Richter decoders and coders/decoders obtained through optimization based on genetic algorithms is substantiated for SEC-DAEC codes.

Global EDF scheduling for parallel real-time tasks

As multicore processors become ever more prevalent, it is important for real-time programs to take advantage of intra-task parallelism in order to support computation-intensive applications with tight deadlines. In this paper, we consider the global earliest deadline first (GEDF) scheduling policy for task sets consisting of parallel tasks. Each task can be represented by a directed acyclic graph (DAG) where nodes represent computational work and edges represent dependences between nodes. In this model, we prove that GEDF provides a capacity augmentation bound of $$4-\frac{2}{m}$$ and a resource augmentation bound of $$2-\frac{1}{m}$$ . The capacity augmentation bound acts as a linear-time schedulability test since it guarantees that any task set with total utilization of at most $$m/(4-\frac{2}{m})$$ where each task’s critical-path length is at most $$1/(4-\frac{2}{m})$$ of its deadline is schedulable on $$m$$ cores under GEDF. In addition, we present a pseudo-polynomial time fixed-point schedulability test for GEDF; this test uses a carry-in work calculation based on the proof for the capacity bound. Finally, we present and evaluate a prototype platform—called PGEDF—for scheduling parallel tasks using global earliest deadline first (GEDF). PGEDF is built by combining the GNU OpenMP runtime system and the $$\text {LITMUS}^\text {RT}$$ operating system. This platform allows programmers to write parallel OpenMP tasks and specify real-time parameters such as deadlines for tasks. We perform two kinds of experiments to evaluate the performance of GEDF for parallel tasks. (1) We run numerical simulations for DAG tasks. (2) We execute randomly generated tasks using PGEDF. Both sets of experiments indicate that GEDF performs surprisingly well and outperforms an existing scheduling techniques that involves task decomposition.

PRE-RESOLVE AND SENSE ADIABATIC LOGIC FOR 100 KHZ TO 500 MHZ FREQUENCY CLASSES

The novel pre-resolve and Sense Adiabatic Logic (PSAL) is a less complex quasi-adiabatic logic circuit usable for frequency range from 100 KHz to 500 MHz. It employs a large height pre-resolved nMOS structured tree and a differential sensing logic. The logic realizes superior energy efficiency through reduced silicon area requirement, low circuit latency, glitch-free output and less switching transients. Significant reduction in switched capacitance realizes enhanced speed performance. Furthermore, evaluation of more than one level of gate (or a complex gate) in each phase makes use of less number of buffers possible, in the adiabatic pipeline. With circuit latency being a major impediment of four-phase adiabatic logic styles, PSAL achieves better throughput and reduced critical path length leading to improved frequency performance. The nMOS structured cascode tree and differential sensing logic help overcome the incomplete charge-recovery and the floating output node problems prevalent in adiabatic logic structures. Full custom and modular flow is adopted in the circuit designs. The design is proved energy-efficient for both low and high frequency ranges of the order of 200 KHz and 500 MHz, respectively for an 8-bit multiplier. Full-custom designs are done using 350 nm CMOS technology library from Austria Micro Systems. Performance efficiency is proved through comparisons with static CMOS and PFAL equivalent circuits through extensive post-layout simulations.

On the Complexity of Nonoverlapping Multivariate Marginal Bounds for Probabilistic Combinatorial Optimization Problems

Given a combinatorial optimization problem with an arbitrary partition of the set of random objective coefficients, we evaluate the tightest-possible bound on the expected optimal value for joint distributions consistent with the given multivariate marginals of the subsets in the partition. For univariate marginals, this bound was first proposed by Meilijson and Nadas [Meilijson, I., A. Nadas. 1979. Convex majorization with an application to the length of critical path. J. Appl. Probab. 16(3) 671–677]. We generalize the bound to nonoverlapping multivariate marginals using multiple-choice integer programming. New instances of polynomial-time computable bounds are identified for discrete distributions. For the problem of selecting up to M items out of a set of N items of maximum total weight, the multivariate marginal bound is shown to be computable in polynomial time, when the size of each subset in the partition is O(log N). For an activity-on-arc PERT network, the partition is naturally defined by subsets of incoming arcs into nodes. The multivariate marginal bound on expected project duration is shown to be computable in time polynomial in the maximum number of scenarios for any subset and the size of the network. As an application, a polynomial-time solvable two-stage stochastic program for project crashing is identified. An important feature of the bound developed in this paper is that it is exactly achievable by a joint distribution, unlike many of the existing bounds.

Look-Up Table Based Implementations of SHA-3 Finalists: JH, Keccak and Skein

Cryptographic hash functions are widely used in many information security applications like digital signatures, message authentication codes (MACs), and other forms of authentication. In response to recent advances in cryptanalysis of commonly used hash algorithms, National Institute of Standards and Technology (NIST) announced a publicly open competition for selection of new standard Secure Hash Algorithm called SHA-3. One important aspect of this competition is evaluation of hardware performances of the candidates. In this work we present efficient hardware implementations of SHA-3 finalists: JH, Keccak and Skein. We propose high speed architectures using Look-Up Table (LUT) resources on FPGAs, to minimize chip area and to reduce critical path lengths. This approach allows us to design data paths of SHA-3 finalists with minimum resources and higher clock frequencies. We implemented and investigated the performance of these candidates on modern and latest FPGA devices from Xilinx. This work serves as performance investigation of leading SHA-3 finalists on most up-to-date FPGAs.

A note on generating finer-grain parallelism in a representation tree

SUMMARY The representation tree lies at the heart of the algorithm of Multiple Relatively Robust Representations for computing orthogonal eigenvectors of a symmetric tridiagonal matrix without Gram–Schmidt. A representation tree describes the incremental shift relations between relatively robust representations of eigenvalue clusters of an unreduced tridiagonal matrix, which are needed to strongly separate close eigenvalues in the relative sense. At the bottom of the representation tree, each leaf defines a relatively isolated eigenvalue to high relative accuracy. The shape of the representation tree plays a pivotal role for complexity and available parallelism: a deeper tree consisting of multiple levels of nodes involves tasks associated to more work (i.e., eigenvalue refinement to resolve eigenvalue clusters) and less parallelism (i.e., a longer critical path as well as potential data movement and synchronization). An embarrassingly parallel, ideal tree on the other hand consists of a root and leaves only. As highly parallel hybrid graphics processing unit/multicore platforms with large memory now become available as commodity platforms, exploiting parallelism in traditional algorithms becomes key to modernizing the components of standard software libraries such as LAPACK. This paper focuses on LAPACK's Multiple Relatively Robust Representations algorithm and investigates the critical case where a representation tree contains a long sequential chain of large (fat) nodes that hamper parallelism. This key problem needs to be addressed as it concerns all sorts of computing environments, distributed computing, symmetric multiprocessor, as well as hybrid graphics processing unit/multicore architectures. We present an improved representation tree that often offers a significantly shorter critical path and finer computational granularity of smaller tasks that are easier to schedule. In a study of selected synthetic and application matrices, we show that an average 75% reduction in the length of the critical path and 82% reduction in task granularity can be achieved. Copyright © 2011 John Wiley & Sons, Ltd.

Optimal utilization of available reconfigurable hardware resources

Field programmable gate arrays (FPGAs) are continuously gaining momentum and becoming essential part of today’s digital systems and applications. The growing use of these devices coupled with increasingly more complex and integrated designs necessitates search for techniques in efficient utilization of their internal resources. Standard HDL coding techniques and synthesis tools implement logic to look up table (LUT) based architecture. The resulting design utilizes more area on the chip and some fast and dedicated areas and resources of the chip remain unutilized. This in turn results in slower clock rates and larger critical path lengths, hence the design remains inefficient in terms of both speed and area. In this paper we present and discuss techniques to effectively utilize the FPGA dedicated resources in order to speed up achievable clock rates and reduce the FPGA area utilization. Various useful HDL constructs are presented that utilize dedicated hardware resources of modern Xilinx FPGAs. Optimization techniques are presented with implementation examples and corresponding quantitative performance evaluation. In most of the cases we have achieved 50% reduction in chip area utilization and simultaneously improved timing results significantly.

Efficient and Deterministic Parallel Placement for FPGAs

We describe a parallel simulated annealing algorithm for FPGA placement. The algorithm proposes and evaluates multiple moves in parallel, and has been incorporated into Altera’s Quartus II CAD system. Across a set of 18 industrial benchmark circuits, we achieve geometric average speedups during the quench of 2.7x and 4.0x on four and eight processors, respectively, with individual circuits achieving speedups of up to 3.6x and 5.9x. Over the course of the entire anneal, we achieve speedups of up to 2.8x and 3.7x, with geometric average speedups of 2.1x and 2.4x. Our algorithm is the first parallel placer to optimize for criteria other than wirelength, such as critical path length, and is one of the few deterministic parallel placement algorithms. We discuss the challenges involved in combining these two features and the new techniques we used to overcome them. We also quantify the impact of maintaining determinism on eight cores, and find that while it reduces performance by approximately 15% relative to an ideal speedup of 8.0x, hardware limitations are a larger factor and reduce performance by 30--40%. We then suggest possible enhancements to allow our approach to scale to 16 cores and beyond.

A heuristic method for RCPSP with fuzzy activity times

In this paper, we propose a heuristic method for resource constrained project scheduling problem with fuzzy activity times. This method is based on priority rule for parallel schedule generation scheme. Calculation of critical path in this case requires comparison of fuzzy numbers. Distance based ranking of fuzzy number is used for finding the critical path length and concept of shifting criticality is proposed for some of the special cases. We also propose a measure for finding the non-integer power of a fuzzy number. We discuss some properties of the proposed method. We use an example to illustrate the method.

Impact of high-level transformations within the ROCCC framework

Reconfigurable computers, where one or more FPGAs are attached to a conventional microprocessor, are promising platforms for code acceleration. Despite their advantages, programmability concerns and the lack of efficient design tools/compilers for FPGAs are preventing the technology's widespread adoption. The traditional compiler technology is microprocessor-based-systems-specific and needs to be customized and augmented to address the needs in reconfigurable computing. The challenges are several due to the resources and performance constraints for FPGAs being drastically different than those of microprocessors, and also that compiling for FPGAs requires laying the computation in space by a circuit rather than in time by a sequence of instructions. ROCCC is an optimizing C-to-VHDL compiler specifically targeting the reconfigurable computer platforms. ROCCC includes several high-level optimizations that parallelize and optimize the source code for minimized area and critical path length and maximized throughput. This article presents the effect of ROCCC's high-level transformations on the performance of the generated VHDL output. ROCCC utilizes: (1) several array access optimizations to eliminate redundant memory accesses, (2) procedure-level optimizations to achieve circuit area reductions of up to 88% compared to circuit areas generated from unoptimized codes, (3) loop-level optimizations to increase the throughput, and (4) transformations unique to certain classes of applications. The preceding listed features help ROCCC generate circuits with very large degrees of parallelism capable of very high computation rates.

Thermal spraying of silicon nitride coatings using highly accelerated precursor powder particles

Highly accelerated powder particles obtained by low-frequency pulsed detonation spraying (LFPDS), high-frequency pulsed detonation spraying (HFPDS), and high-current pulsed plasma spraying (HCPPS) were applied with the aim to deposit dense protective silicon nitride coatings that adhere well to steel and nickel superalloy surfaces. The silicon nitride-based feedstock powders comprise α-silicon nitride with sintering additives such as alumina, yttria and minor amounts of aluminum nitride and/or silica and magnesia. Coatings were characterized by testing their critical wear path length, tensile adhesion strength, microindentation hardness, salt-spray corrosion and thermoshock resistances, and friction coefficient (pin-on-disk).

Helper locks for fork-join parallel programming

Helper locks allow programs with large parallel critical sections, called parallel regions, to execute more efficiently by enlisting processors that might otherwise be waiting on the helper lock to aid in the execution of the parallel region. Suppose that a processor p is executing a parallel region A after having acquired the lock L protecting A . If another processor p ′ tries to acquire L , then instead of blocking and waiting for p to complete A , processor p ′ joins p to help it complete A . Additional processors not blocked on L may also help to execute A . The HELPER runtime system can execute fork-join computations augmented with helper locks and parallel regions. HELPER supports the unbounded nesting of parallel regions. We provide theoretical completion-time and space-usage bounds for a design of HELPER based on work stealing. Specifically, let V be the number of parallel regions in a computation, let T 1 be its work, and let T ∞ be its "aggregate span" --- the sum of the spans (critical-path lengths) of all its parallel regions. We prove that HELPER completes the computation in expected time O ( T 1 / P P + T ∞+ PV on P processors. This bound indicates that programs with a small number of highly parallel critical sections can attain linear speedup. For the space bound, we prove that HELPER completes a program using only O ( P S 1 stack space, where S 1 is the sum, over all regions, of the stack space used by each region in a serial execution. Finally, we describe a prototype of HELPER implemented by modifying the Cilk multithreaded runtime system. We used this prototype to implement a concurrent hash table with a resize operation protected by a helper lock.

A Survey of Compute Intensive Algorithms for Ribo Nucleic Acids Structural Detection

Problem statement: Finding an accurate RNA structural alignment from primary sequence due to it is time consuming and computationally NP-hard problem is a major bioinformatics challenge. According to our investigation majority of current researches were concerned on achieving faster execution time, improving space complexity and better cache management. Recently one research introduced cache-efficient Chip Multiprocessor (CMP) algorithms with good speed-up to exploit parallelism in detection the critical path length. Our contribution in this article was a comprehensive survey of methods for solving RNA secondary structure prediction with Pseudoknots (PK) and sequence alignment in bioinformatics. The aim was to highlight the challenges related issues which would provide sufficient information to assist the new coming researchers in this field as well as a good reference guide for bioinformatics professionals. Approach: We computed various algorithms that predicted an RNA molecules secondary structure from primary sequence, without pseudoknots from one side and pseudoknotted RNA secondary structure in the other side. Furthermore, we also reviewed and compared in two tables the methods that developed for RNA structural predictions. Results: Our findings of this survey confirmed that Dynamic Programming (DP) method via CMP algorithms can be used to predict the RNA secondary structure with simple PK and it gives good results. Conclusion: The methods for predicting RNA's structural are coming in two groups: Firstly, pseudoknotted RNA structural problem is computationally complex and secondly, common methods significantly gave not accurate enough results for predicting pseudoknotted RNA.

A novel task scheduling algorithm based on dynamic critical path and effective duplication for pervasive computing environment

AbstractIn order to effectively utilize massive heterogeneous resources and provide transparent computing capability to upper applications, task scheduling as the key issue of pervasive computing system becomes significantly important. Previous proposed priority and duplication based task scheduling algorithms, which can be applied in pervasive computing environment, usually have following limitations: critical path cannot be calculated accurately while neglecting the effect of resource availability in scheduling; in duplication based resource allocation stage, duplications without restriction would lead to some negative effects on final schedule length (SL). For the purpose of solving these problems, a novel task scheduling algorithm based on dynamic critical path (DCP) and effective duplication, called DCPED, is presented in this paper. In DCPED, a more accurate DCP calculation method which takes resource availability into account is introduced. Meanwhile an effective task duplication strategy is proposed to eliminate ineffective duplications and make an optimized schedule result by using space compression technique and dynamic critical path length (DCPL) based evaluation technique respectively. Finally, simulation results show that DCPED can outperform previous algorithms significantly in NSL and speedup rate metrics. Especially, it is very effective for utilizing computing resources and scheduling the fine‐grain and large‐scale workflow applications in pervasive computing system. Copyright © 2008 John Wiley & Sons, Ltd.

Low Power Realization and Synthesis of Higher-Order FIR Filters Using an Improved Common Subexpression Elimination Method

The complexity of Finite Impulse Response (FIR) filters is mainly dominated by the number of adders (subtractors) used to implement the coefficient multipliers. It is well known that Common Subexpression Elimination (CSE) method based on Canonic Signed Digit (CSD) representation considerably reduces the number of adders in coefficient multipliers. Recently, a binary-based CSE (BSE) technique was proposed, which produced better reduction of adders compared to the CSD-based CSE. In this paper, we propose a new 4-bit binary representation-based CSE (BCSE-4) method which employs 4-bit Common Subexpressions (CSs) for implementing higher order low-power FIR filters. The proposed BCSE-4 offers better reduction of adders by eliminating the redundant 4-bit CSs that exist in the binary representation of filter coefficients. The reduction of adders is achieved with a small increase in critical path length of filter coefficient multipliers. Design examples show that our BCSE-4 gives an average power consumption reduction of 5.2% and 6.1% over the best known CSE method (BSE, NR-SCSE) respectively, when synthesized with TSMC-0.18 μm technology. We show that our BCSE-4 offers an overall adder reduction of 6.5% compared to BSE without any increase in critical path length of filter coefficient multipliers.

Leakage-Aware Multiprocessor Scheduling

When peak performance is unnecessary, Dynamic Voltage Scaling (DVS) can be used to reduce the dynamic power consumption of embedded multiprocessors. In future technologies, however, static power consumption due to leakage current is expected to increase significantly. Then it will be more effective to limit the number of processors employed (i.e., turn some of them off), or to use a combination of DVS and processor shutdown. In this paper, leakage-aware scheduling heuristics are presented that determine the best trade-off between these three techniques: DVS, processor shutdown, and finding the optimal number of processors. Experimental results obtained using a public benchmark set of task graphs and real parallel applications show that our approach reduces the total energy consumption by up to 46% for tight deadlines (1.5× the critical path length) and by up to 73% for loose deadlines (8× the critical path length) compared to an approach that only employs DVS. We also compare the energy consumed by our scheduling algorithms to two absolute lower bounds, one for the case where all processors continuously run at the same frequency, and one for the case where the processors can run at different frequencies and these frequencies may change over time. The results show that the energy reduction achieved by our best approach is close to these theoretical limits.

Critical Path Analysis With Fuzzy Activity Times

Fuzzy logic has been proposed as an alternate approach for quantifying uncertainty relating to project activity duration. The fuzzy logic approach may be suitable in the situations where past data are either unavailable or not relevant, the definition of the activity itself is somewhat unclear, or the notion of the activity's completion is vague. The purpose of this paper is to present a new methodology for fuzzy critical path analysis that is consistent with the extension principle of fuzzy logic. It is the direct generalization of critical path analysis to the fuzzy domains, and resolves some of the problems expressed in the fuzzy critical path literature, especially in computing the fuzzy backward pass of the project network and fuzzy activity criticality. Here the uncertainty is represented by three possible time estimates in a way that is similar to the well-known program evaluation and review technique (PERT) approach. Another important advantage of the proposed approach is that one integrated procedure determines both the fuzzy set of critical path lengths and fuzzy activity criticality. The proposed approach constructs the membership function for the fuzzy set of critical path lengths and the fuzzy activity criticality by solving a series of mathematical programming problems. The proposed method is successfully tested on well-known problem sets, and is shown to offer computation times that should allow it to help project managers better understand and manage project schedule uncertainty.

A New Common Subexpression Elimination Algorithm for Realizing Low-Complexity Higher Order Digital Filters

The complexity of linear-phase finite-impulse-response (FIR) filters is dominated by the complexity of coefficient multipliers. The number of adders (subtractors) used to implement the multipliers determines the complexity of the FIR filters. It is well known that common subexpression elimination (CSE) methods based on canonical signed digit (CSD) coefficients reduce the number of adders required in the multipliers of FIR filters. A new CSE algorithm using binary representation of coefficients for the implementation of higher order FIR filters with a fewer number of adders than CSD-based CSE methods is presented in this paper. We show that the CSE method is more efficient in reducing the number of adders needed to realize the multipliers when the filter coefficients are represented in the binary form. Our observation is that the number of unpaired bits (bits that do not form CSs) is considerably few for binary coefficients compared to CSD coefficients, particularly for higher order FIR filters. As a result, the proposed binary-coefficient-based CSE method offers good reduction in the number of adders in realizing higher order filters. The reduction of adders is achieved without much increase in critical path length of filter coefficient multipliers. Design examples of FIR filters show that our method offers an average adder reduction of 18% over the best known CSE method, without any increase in the logic depth.

Vulnerability Assessment of Power Grid Using Graph Topological Indices

This paper presents an assessment of the vulnerability of the power grid to blackout using graph topological indexes. Based on a FERC 715 report and the outage reports, the cascading faults of summer WSCC 1996 are reconstructed, and the graphical property of the grid is compared between two cases: when the blackout triggering lines are removed simulating the actual sequence of cascading outages and when the same number of randomly selected lines are removed. The investigation finds that the critical path lengths of the triggering events of the July and August outages of 1996 WSCC blackout are higher than those of no-outage and arbitrary events. In addition, the small world-ness index for each of the outage triggering events is much smaller than that of normal or any no-outage scenario, indicating that events of shifting a network from small world to a random network would be more likely cascaded to wide area outage.

A Highly Parallel Joint VLSI Architecture for Transforms in H.264/AVC

In H.264/AVC, the concept of adapting the transform size to the block size of motion-compensated prediction residue has proven to be an important coding tool. This paper presents highly parallel joint circuit architecture for 8?×?8 and 4?×?4 adaptive block-size transforms in H.264/AVC. By decomposing the 8?×?8 transform to basic 4?×?4 transforms, a unified architecture is designed for both 8?×?8 and 4?×?4 transform and the transform data-path can be efficiently reused for six kinds of transforms. i.e., 8?×?8 forward, 8?×?8 inverse, 4?×?4 forward, 4?×?4 inverse, forward-Hadamard, inverse-Hadamard transforms. Linear shift mapping is applied on the memory buffer to support parallel access both in row and column directions which eliminates the need for a transpose circuit. For reusable and configurable transform data-path, a multiple-stage pipeline is designed to reduce the critical path length and increase throughput. The design is implemented under UMC 0.18 um technology at 200 MHz with 13.651 K logic gates, which can support 1,920?×?1,088 30 fps H.264/AVC HDTV decoder.