CPU Design Research Articles

Design and Implementation of Digital Integrated Circuit Based CPU

This paper presents a simplified 16-bit CPU design and its implementation using digital integrated circuits developed with Verilog hardware description language, while emphasizing simulation through the EDA tool. This design puts more emphasis on the critical roles played by the data path and the control unit, executing key instructions including arithmetic operations such as addition, subtraction, bitwise logic, and conditional jumps. This structurally modular CPU is both functioning and stable in nature, allowing support for future enhancements and enhancements as well, thereby serving as an effective model towards an understanding of the principles of CPU design. The execution of these basic instructions puts the core of the CPU under test and reaffirms its proper operation in respect of the detailed instruction set, while its extensibility design confirms further improvement possibilities for future complex instructions as well as finite-state machine optimization for the control unit. The present work not only proves the possibility of creating a fully working CPU, using readily available bare minimum resources to implement a prototype, but is also a breakthrough in future research with CPU architecture. The obtained results will shed light on CPU functionality optimization and extension, being the ground for building more powerful and effective processors in the future.

Multi-zero pole dynamically compensated LDO with low quiescent current

This paper presents an LDO design tailored to the various power domains of CPUs. In contemporary CPU designs, different functional modules typically necessitate distinct voltage levels, thus requiring a flexible and adjustable power management approach. An LDO with an internally compensated super source follower (SSF) and a multi-zero-pole compensated loop stability is proposed. The SSF is used to reduce the output impedance of the LDO, enhancing its carry-under-load capability. The loop is then transformed into a multi-zero-pole system through Miller compensation, feed-forward compensation, and zero-pole tracking compensation techniques, enabling the LDO to achieve stability and reliability under different loads. The LDO proposed in this study was designed using a 110 nm CMOS process. The LDO can operate within a temperature range of −40–150 °C, with a low quiescent current of 57 μA. The power supply rejection ratio of the circuit is −22 dB at 1 MHz. When the load current jumps from 5 mA to 300 mA within 40 μs, the output voltage experiences an undershoot of 271 mV, an overshoot of 174 mV, and a maximum adjustment time of 100 μs. The load regulation is 0.00267 mV/mA, and the line regulation is 1 mV/V.

Design and Evaluation of CPU-, GPU-, and FPGA-Based Deployment of a CNN for Motor Imagery Classification in Brain-Computer Interfaces

Brain–computer interfaces (BCIs) have gained popularity in recent years. Among noninvasive BCIs, EEG-based systems stand out as the primary approach, utilizing the motor imagery (MI) paradigm to discern movement intentions. Initially, BCIs were predominantly focused on nonembedded systems. However, there is now a growing momentum towards shifting computation to the edge, offering advantages such as enhanced privacy, reduced transmission bandwidth, and real-time responsiveness. Despite this trend, achieving the desired target remains a work in progress. To illustrate the feasibility of this shift and quantify the potential benefits, this paper presents a comparison of deploying a CNN for MI classification across different computing platforms, namely, CPU-, embedded GPU-, and FPGA-based. For our case study, we utilized data from 29 participants included in a dataset acquired using an EEG cap for training the models. The FPGA solution emerged as the most efficient in terms of the power consumption–inference time product. Specifically, it delivers an impressive reduction of up to 89% in power consumption compared to the CPU and 71% compared to the GPU and up to a 98% reduction in memory footprint for model inference, albeit at the cost of a 39% increase in inference time compared to the GPU. Both the embedded GPU and FPGA outperform the CPU in terms of inference time.

Numerical study optimation design of CPU cooling system analysis using CFD method

Computers often experience damage to the CPU, especially the mainboard and processor, due to several factors, including human error or excessive use and environmental conditions. Component placement is frequently utilized to improve the CPU room conditions to keep it cool. This research numerically investigates desktop PC processors and heatsink configurations for mechanical engineering vocational learning. The kind of metal material, number of fans, and fan arrangement were all tested at three levels. The computer components in this research are the CPU, heatsink, fan, and processor—a 65-watt Thermal Design Power (TDP) CPU with a constant air intake speed of 5 m/s. The criteria investigated include metal type (steel, aluminum, and copper), cooling design (horizontal, vertical, and mixed), and fan count (2-4-8). The methods used in this research are the Computational Fluid Dynamics (CFD) method and the Taguchi method to examine fluid flow characteristics and temperature. Numerical results show the maximum temperature is 123 °C in the vertical, eight-fan, and steel configurations. Minimum temperature 39.22 °C in mixed configuration, eight fans, and copper. These findings reveal that the kind of metal material, number of fans, and fan arrangement all impact the CPU cooler and heatsink configuration. However, the Taguchi method can provide a more detailed understanding of configuration.

AMNES: Accelerating the Computation of Data Correlation Using FPGAs

A widely used approach to characterize input data in both databases and ML is computing the correlation between attributes. The operation is supported by all major database engines and ML platforms. However, it is an expensive operation as the number of attributes involved grows. To address the issue, in this paper we introduce AMNES, a stream analytics system offloading the correlation operator into an FPGA-based network interface card. AMNES processes data at network line rate and the design can be used in combination with smart storage or SmartNICs to implement near data or in-network data processing. AMNES design goes beyond matrix multiplication and offers a customized solution for correlation computation bypassing the CPU. Our experiments show that AMNES can sustain streams arriving at 100 Gbps over an RDMA network, while requiring only ten milliseconds to compute the correlation coefficients among 64 streams, an order of magnitude better than competing CPU or GPU designs.

Efficient Arithmetic Block Identification With Graph Learning and Network-Flow

Arithmetic block identification in gate-level netlists plays an essential role for various purposes, including malicious logic detection, functional verification, or macro-block optimization. However, current methods usually suffer from either low performance or poor scalability. To address the issue, we come up with a novel framework based on graph learning and network flow analysis, that extracts desired logic components from a complete circuit netlist. We design a novel asynchronous bidirectional graph neural network (ABGNN) dedicated to representation learning on directed acyclic graphs. In addition, we develop a convex cost network-flow-based datapath extraction approach to match the predicted block inputs with predicted block outputs. Experimental results on open-source RISC-V CPU designs demonstrate that our proposed solution significantly outperforms several state-of-the-art arithmetic block identification flows.

Design of a nonvolatile-register-embedded RISC-V CPU with software-controlled data-retention and hardware-acceleration functions

This paper describes the design of a nonvolatile CPU based on RISC-V that is an open-source and highly flexible instruction set architecture. This CPU incorporates nonvolatile registers utilizing magnetic tunnel junction (MTJ) device, as well as custom instructions specific to the control of these nonvolatile registers and an accelerator module embedded into the CPU architecture. These techniques enable efficient execution of intermittent operations suitable for energy-limited internet-of-things (IoT) applications. Through performance evaluation of the CPU designed in a 55-nm CMOS/MTJ-hybrid process technology, we show that our CPU can save up to 56.9% of power consumption compared to conventional ones, with an average power consumption of 3.91 μW/MHz.

FPGA-based LoongArch Five-stage Pipeline CPU

We designed and implemented a five-stage pipeline CPU based on the FPGA platform, programmed in Verilog hardware description language to implement LoongArch architecture. The design and implementation of the Instruction Fetch (IF) stage, Instruction Decode (ID) stage, Instruction Execute (EX) stage, Memory Access (MEM) stage, and Write Back (WB) stage. The design and implementation of the important modules in the pipeline are given. The use of the Bubble method and Bypass technique solves most of the parameter passing problems and branch judgment problems in the pipeline. The access memory problem is solved using design tricks. Finally, the design is verified on an FPGA platform. The CPU design can be well used in learning and research related to pipeline CPUs. It can also support experimental platforms and provide an example for further research in pipelines and SOCs.

Design and Implementation of High Speed and Area Optimized Vedic Processor for Embedded Systems

The proposed work on the design and implementation of a High-Speed and Area-Optimized Vedic Processor for Embedded Systems appears promising. Here's an outline that we might find useful for organizing our work. Discuss briefly the growing need for high-performance embedded systems and the crucial role of processors. Summarize prior research on Vedic Processors, highlighting major features and optimizations gained by earlier researchers. The exact Vedic mathematics ideas and sutras that we propose to exploit in our processor design. Detail tactics for obtaining high-speed operations in the CPU, taking into account parallelism, pipelining, and other optimization approaches. As the computational complexity of tiny battery-powered devices develops, this study addresses the need for a fast 16-bit RISC processor. The emphasis is on boosting processor capabilities by integrating a Multiply-Accumulator (MAC) unit based on Vedic mathematics. The inclusion of a new instruction set involves VHDL-based changes to the processor's architecture, to ensure simplicity and total compatibility with the current structure. This study describes an innovative strategy for enhancing the capabilities of modest 16-bit RISC processors by including a Vedic mathematics-based Multiply-Accumulator (MAC) unit. The objective is to improve processor functionality by providing a new instruction set, which will be performed through VHDL-based changes to the CPU's design. The newly designed instruction set keeps its structure basic, ensuring complete compatibility with the previous architecture. A 16-bit pipelined system based on Harvard design has several components in its pipeline, comprising register access, arithmetic execution, front-end logic execution, instruction fetch, and decode. The simulation results demonstrate the validity of the proposed design, demonstrating effective verification and synthesis of the MAC architecture on an FPGA platform.

CREATING MULTITHREADED PTOGRAMS IN C++

For many years, the increase in computing power of modern devices is achieved not by increasing the clock frequency and bandwidth of CPUs, but by using hyper-threaded and multicore architectures. This simple change in approach to the CPU design led to dramatic changes in the organization of computing and became a turning point for software developers. Software that is going to take advantage of the increased computing power of multi-core architectures must be designed to be able to perform multiple tasks simultaneously. When covering the topic of parallel/simultaneous computing, scientists and IT professionals use two terms: (1) parallelism and (2) concurrency. A third important term when considering parallel/simultaneous computing is “multithreading”. In C++, the two most common ways to implement parallelism are concurrency and parallelism itself. Although they can be used in other programming languages, C++ stands out for its ability to use concurrent computations with lower-than-average utilization of general machine resources, as well as its ability to execute complex instructions. The C++11 standard introduced support for multi-threaded programs. The C++ standard recognized the existence of multithreading in the language and provided components for writing multithreaded programs in the <thread> library. This made it possible to write multithreaded programs in C++ without relying on platform-specific extensions and enabled the creation of portable multithreaded code with guaranteed behavior. The <thread> library provides extensive opportunities for organizing parallel and concurrent calculations, it also contains the C++ memory model, conditional variables, mutexes, etc. for thread synchronization. The article analyzes the possibilities of writing programs in the C++ using multiple threads for parallel and concurrent execution of tasks. It also considers the features of the C++ and the tools of the <thread> library that make parallelism and concurrency possible.

Accelerating Bayesian Neural Networks via Algorithmic and Hardware Optimizations

Bayesian neural networks (BayesNNs) have demonstrated their advantages in various safety-critical applications, such as autonomous driving or healthcare, due to their ability to capture and represent model uncertainty. However, standard BayesNNs require to be repeatedly run because of Monte Carlo sampling to quantify their uncertainty, which puts a burden on their real-world hardware performance. To address this performance issue, this article systematically exploits the extensive structured sparsity and redundant computation in BayesNNs. Different from the unstructured or structured sparsity in standard convolutional NNs, the structured sparsity of BayesNNs is introduced by Monte Carlo Dropout and its associated sampling required during uncertainty estimation and prediction, which can be exploited through both algorithmic and hardware optimizations. We first classify the observed sparsity patterns into three categories: channel sparsity, layer sparsity and sample sparsity. On the algorithmic side, a framework is proposed to automatically explore these three sparsity categories without sacrificing algorithmic performance. We demonstrated that structured sparsity can be exploited to accelerate CPU designs by up to 49 times, and GPU designs by up to 40 times. On the hardware side, a novel hardware architecture is proposed to accelerate BayesNNs, which achieves a high hardware performance using the runtime adaptable hardware engines and the intelligent skipping support. Upon implementing the proposed hardware design on an FPGA, our experiments demonstrated that the algorithm-optimized BayesNNs can achieve up to 56 times speedup when compared with unoptimized Bayesian nets. Comparing with the optimized GPU implementation, our FPGA design achieved up to 7.6 times speedup and up to 39.3 times higher energy efficiency.

Network topology-directed design of molecular CPU for cell-like dynamic information processing.

Natural cells (NCs) can automatically and continuously respond to fluctuant external information and distinguish meaningful stimuli from weak noise depending on their powerful genetic and protein networks. We herein report a network topology–directed design of dynamic molecular processing system (DMPS) as a molecular central processing unit that powers an artificial cell (AC) able to process fluctuant information in its immediate environment similar to NCs. By constructing a mixed cell community, ACs and NCs have synchronous response to fluctuant extracellular stimuli under physiological condition and in a blood vessel–mimic circulation system. We also show that fluctuant bioinformation released by NCs can be received and processed by ACs. The molecular design of DMPS-powered AC is expected to allow a profound understanding of biological systems, advance the construction of intelligent molecular systems, and promote more elegant bioengineering applications.

Exploring HW/SW Co-Design for Video Analysis on CPU-FPGA Heterogeneous Systems

Deep neural network (DNN)-based video analysis has become one of the most essential and challenging tasks to capture implicit information from video streams. Although DNNs significantly improve the analysis quality, they introduce intensive compute and memory demands and require dedicated hardware for efficient processing. The customized heterogeneous system is one of the promising solutions with general-purpose processors (CPUs) and specialized processors (DNN Accelerators). Among various heterogeneous systems, the combination of CPU and FPGA has been intensively studied for DNN inference with improved latency and energy consumption compared to CPU &#x002B; GPU schemes and with increased flexibility and reduced time-to-market cost compared to CPU &#x002B; ASIC designs. However, deploying DNN-based video analysis on CPU &#x002B; FPGA systems still presents challenges from the tedious RTL programming, the intricate design verification, and the time-consuming design space exploration. To address these challenges, we present a novel framework, called EcoSys, to explore co-design and optimization opportunities on CPU-FPGA heterogeneous systems for accelerating video analysis. Novel technologies include 1) a coherent memory space shared by the host and the customized accelerator to enable efficient task partitioning and online DNN model refinement with reduced data transfer latency; 2) an end-to-end design flow that supports high-level design abstraction and allows rapid development of customized hardware accelerators from Python-based DNN descriptions; 3) a design space exploration (DSE) engine that determines the design space and explores the optimized solutions by considering the targeted heterogeneous system and user-specific constraints; and 4) a complete set of co-optimization solutions, including a layer-based pipeline, a feature map partition scheme, and an efficient memory hierarchical design for the accelerator and multithreading programming for the CPU. In this article, we demonstrate our design framework to accelerate the long-term recurrent convolution network (LRCN), which analyzes the input video and output one semantic caption for each frame. EcoSys can deliver 314.7 and 58.1 frames/s by targeting the LRCN model with AlexNet and VGG-16 backbone, respectively. Compared to the multithreaded CPU and pure FPGA design, EcoSys achieves <inline-formula> <tex-math notation="LaTeX">$20.6\times $ </tex-math></inline-formula> and <inline-formula> <tex-math notation="LaTeX">$5.3\times $ </tex-math></inline-formula> higher throughput performance.

Hints on the Multicore CPU Design for Personal Computers

Abstract Abstract - Multi-core processors are created by combining multiple units, each called the core, containing the processing unit, registers and a cache. This study provides a detailed analysis on the performances of multicore CPUs for personal computers. We parallelized some cryptographic algorithms with OpenMP tool and tested one 2-core and one 4-core CPU with two cryptographic software one of which imposes high data load and the other one high work load. In the light of the experiments that stress the CPUs from these two different aspects, we present our hints and suggestions for designing multicore chips for the usage in personal computers.

Topology optimization of multimaterial distribution based on isogeometric boundary element and piecewise constant level set method

Based on isogeometric boundary element method (IGA BEM) and piecewise constant level set (PCLS) method, a new topology optimization approach is proposed to design the distribution of sound absorbing materials (SAMs) on structural surfaces. First, an efficient IGA BEM is developed with the combination of multipatch discretization and parallel CPU design. A complex submarine model comprising multiple non-uniform rational B-spline surfaces is built for engineering optimization design. Second, the PCLS method is applied to represent the multiple SAM domains without gray elements, and the sensitivities of the objective function with respect to PCLS functions are obtained using the adjoint variable method. Finally, the optimization algorithm based on PCLS method is improved by a novel penalty coefficient formulation and ordered volume constraints. The improved optimization algorithm can realize the control of multimaterial volume fractions and make the objective function steadily converge for different volume structures without the need to change any parameters. The accuracy, efficiency, and applicability of the proposed approach in engineering are demonstrated by several numerical examples.

Design of RISC-V CPU for 100 Gbps Network Application

<p indent=0mm>As a new open-source reduced instruction set architecture, RISC-V has advantages of low power consumption, small area and high performance. Therefore, technology and products based on RISC-V are developing rapidly. However, currently there are few medium and high end 64 bit CPU design instances based on the RISC-V architecture, and it is also hard to find corresponding commercial IP, especially for high-speed network applications. In this paper, we firstly improved the open source 64 bit U500 RISC-V SoC by extending the Bus width and adding L2 Cache, and etc. Secondly we implemented a complete 100 Gbps Ethernet function, which includes MAC, PCS, and SerDes, and the TX buffer and RX buffer used for the function. Finally we proved correctness and effectiveness of entire 64 bit RISC-V CPU design and 100 Gbps Ethernet function by simulation, FPGA verification and boot of Linux operation system. The designed RISC-V CPU and 100 Gbps Ethernet function can be applied to data center application such as smart network interface cards.

Sustainable computing

Energy consumption by computers is expanding exponentially along with big data and AI processing. The trend can be broken by adopting alternate approaches to CPU and GPU design. Specifically, Adiabatic Reversible Logic (ARL) has been proposed as the solution. This essay surveys the technology of ARL and gives early examples of actual reversible machines.

Numerical and experimental study on optimization of CPU system cooled by nanofluids

To improve CPU cooling performance, TiO2-water nanofluids with volume concentration 9% were used as the cooling mediumin. Nanofluids inlet and outlet positions play a crucial influence on the cooling performance, to further optimize the cooling property, the influence of nanofluids inlet and outlet positions (top and two side) on CPU cooling performance was numerically and experimentally studied by a two-phase lattice Boltzmann model and an experimental method respectively. The numerical simulation outcomes fit well with the experimental outcomes. Outcomes indicated that nanofluids can effectively reduce the average temperature of CPU by 4.54 °C at best in comparison with water under the identical operating conditions. CPU with inlet and outlet at top can reduce the average temperature by 8.49 °C at most compared with that at both two sides, and CPU temperature distribution is more uniform when inlet and outlet locate at top of CPU. Inlet and outlet at top are more suitable for CPU cooling. The results provide some guidance for the design of CPU cooling experiment system.

Dynamic Undervolting to Improve Energy Efficiency on Multicore X86 CPUs

Chip manufacturers introduce redundancy at various levels of CPU design to guarantee correct operation, even for worst-case combinations of non-idealities in process variation and system operating conditions. This redundancy is implemented partly in the form of voltage margins. However, for a wide range of real-world execution scenarios these margins are excessive and merely translate to increased power consumption, hindering the effort towards higher energy efficiency in both HPC and general purpose computing. Our study on the x86-64 Haswell and Skylake multicore microarchitectures reveals wide voltage margins, which vary across different microarchitectures, different chip parts of the same microarchitecture, and across different workloads. We find that it is necessary to quantify voltage margins using multi-threaded and multi-instance workloads, as characterization with single-threaded and single-instance workloads that do not stress the CPU to its full capacity typically identifies overly optimistic margins that lead to errors when applied in realistic program execution scenarios. In addition, we introduce, deploy and evaluate a run-time governor that dynamically reduces the supply voltage of modern multicore x86-64 CPUs. Our governor employs a model that takes as input a set of performance metrics which are directly measurable via performance monitoring counters and have high predictive value for the minimum tolerable supply voltage ( $V_{min}$ V m i n ), to predict and apply the appropriate reduction for the workload at hand. Compared with the conventional DVFS governor, our approach achieves up to 42 percent energy savings for the Skylake family and 34 percent for the Haswell family for complex, real-world applications.

Optimizing Server Refresh Cycles: The Case for Circular Economy With an Aging Moore's Law

Demand for digital services is increasing significantly. Addressing energy efficiency at the data center mechanical and electrical infrastructure level is starting to suffer from the law of diminishing returns. IT equipment, specifically servers, account for a significant part of the overall facility energy consumption and environmental impact, and thus, present a major opportunity, not the least from a circular economy perspective. To reduce the environmental impact of servers, it is important to realize the effect of manufacturing, operating, and disposing of servers on the environment. This work presents new insights into the effect of refreshing servers with remanufactured and refurbished servers on energy efficiency and the environment. The research takes into consideration the latest changes in CPU design trends and Moore's law. The study measures and analyzes the use phase energy consumption of remanufactured servers vs new servers with various hardware configurations. Case studies are used to evaluate the potential impact of refurbished server refresh from an economic as well as environmental perspectives.